Update to SDM 2.2:
o Add tf (test feature) instruction, o Add vmsw (VM switch) instruction. While here, update copyright. MFC after: 1 week
This commit is contained in:
Marcel Moolenaar
parent
f1bf5adef5
commit
0705941372
@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2000-2003 Marcel Moolenaar
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* Copyright (c) 2000-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -110,6 +110,7 @@ enum asm_cmpltr_class {
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ASM_CC_RW,
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ASM_CC_TREL, ASM_CC_TRUNC,
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ASM_CC_UNIT, ASM_CC_UNPACK, ASM_CC_UNS,
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ASM_CC_VMSW,
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ASM_CC_XMA
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};
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@ -212,7 +213,7 @@ enum asm_fmt {
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ASM_FMT_I17, ASM_FMT_I18, ASM_FMT_I19, ASM_FMT_I20,
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ASM_FMT_I21, ASM_FMT_I22, ASM_FMT_I23, ASM_FMT_I24,
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ASM_FMT_I25, ASM_FMT_I26, ASM_FMT_I27, ASM_FMT_I28,
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ASM_FMT_I29,
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ASM_FMT_I29, ASM_FMT_I30,
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ASM_FMT_M = 0x0500,
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ASM_FMT_M1, ASM_FMT_M2, ASM_FMT_M3, ASM_FMT_M4,
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ASM_FMT_M5, ASM_FMT_M6, ASM_FMT_M7, ASM_FMT_M8,
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@ -274,9 +275,10 @@ enum asm_op {
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ASM_OP_ST2, ASM_OP_ST4, ASM_OP_ST8, ASM_OP_STF, ASM_OP_STF8,
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ASM_OP_STFD, ASM_OP_STFE, ASM_OP_STFS, ASM_OP_SUB, ASM_OP_SUM,
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ASM_OP_SXT1, ASM_OP_SXT2, ASM_OP_SXT4, ASM_OP_SYNC,
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ASM_OP_TAK, ASM_OP_TBIT, ASM_OP_THASH, ASM_OP_TNAT, ASM_OP_TPA,
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ASM_OP_TTAG,
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ASM_OP_TAK, ASM_OP_TBIT, ASM_OP_TF, ASM_OP_THASH, ASM_OP_TNAT,
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ASM_OP_TPA, ASM_OP_TTAG,
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ASM_OP_UNPACK1, ASM_OP_UNPACK2, ASM_OP_UNPACK4,
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ASM_OP_VMSW,
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ASM_OP_XCHG1, ASM_OP_XCHG2, ASM_OP_XCHG4, ASM_OP_XCHG8, ASM_OP_XMA,
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ASM_OP_XOR,
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ASM_OP_ZXT1, ASM_OP_ZXT2, ASM_OP_ZXT4,
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2000-2003 Marcel Moolenaar
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* Copyright (c) 2000-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -567,6 +567,12 @@ asm_decodeB(uint64_t ip, struct asm_bundle *b, int slot)
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case 0x10:
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op = ASM_OP_EPC, fmt = ASM_FMT_B8;
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break;
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case 0x18:
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op = ASM_OP_VMSW_0, fmt = ASM_FMT_B8;
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break;
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case 0x19:
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op = ASM_OP_VMSW_1, fmt = ASM_FMT_B8;
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break;
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case 0x20:
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switch (FIELD(bits, 6, 3)) { /* btype */
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case 0x0:
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@ -1000,11 +1006,20 @@ asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot)
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fmt = ASM_FMT_I16;
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break;
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case 0x2:
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op = ASM_OP_TNAT_Z, fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_Z,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_Z,
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fmt = ASM_FMT_I30;
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break;
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case 0x3:
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op = ASM_OP_TNAT_Z_UNC,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_Z_UNC,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_Z_UNC,
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fmt = ASM_FMT_I30;
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break;
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}
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} else {
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@ -1018,12 +1033,20 @@ asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot)
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fmt = ASM_FMT_I16;
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break;
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case 0x2:
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op = ASM_OP_TNAT_Z_AND,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_Z_AND,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_Z_AND,
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fmt = ASM_FMT_I30;
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break;
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case 0x3:
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op = ASM_OP_TNAT_NZ_AND,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_NZ_AND,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_NZ_AND,
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fmt = ASM_FMT_I30;
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break;
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}
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}
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@ -1040,12 +1063,20 @@ asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot)
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fmt = ASM_FMT_I16;
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break;
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case 0x2:
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op = ASM_OP_TNAT_Z_OR,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_Z_OR,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_Z_OR,
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fmt = ASM_FMT_I30;
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break;
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case 0x3:
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op = ASM_OP_TNAT_NZ_OR,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_NZ_OR,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_NZ_OR,
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fmt = ASM_FMT_I30;
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break;
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}
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} else {
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@ -1059,12 +1090,20 @@ asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot)
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fmt = ASM_FMT_I16;
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break;
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case 0x2:
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op = ASM_OP_TNAT_Z_OR_ANDCM,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_Z_OR_ANDCM,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_Z_OR_ANDCM,
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fmt = ASM_FMT_I30;
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break;
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case 0x3:
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op = ASM_OP_TNAT_NZ_OR_ANDCM,
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fmt = ASM_FMT_I17;
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if (FIELD(bits, 19, 1) == 0) /* x */
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op = ASM_OP_TNAT_NZ_OR_ANDCM,
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fmt = ASM_FMT_I17;
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else
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op = ASM_OP_TF_NZ_OR_ANDCM,
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fmt = ASM_FMT_I30;
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break;
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}
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}
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2000-2003 Marcel Moolenaar
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* Copyright (c) 2000-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -1660,6 +1660,46 @@ asm_normalize(struct asm_inst *i, enum asm_op op)
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_UNC);
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op = ASM_OP_TBIT;
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break;
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case ASM_OP_TF_NZ_AND:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_NZ);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_AND);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_NZ_OR:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_NZ);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_OR);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_NZ_OR_ANDCM:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_NZ);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_OR_ANDCM);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_Z:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_Z);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_NONE);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_Z_AND:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_Z);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_AND);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_Z_OR:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_Z);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_OR);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_Z_OR_ANDCM:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_Z);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_OR_ANDCM);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TF_Z_UNC:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_Z);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_UNC);
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op = ASM_OP_TF;
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break;
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case ASM_OP_TNAT_NZ_AND:
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asm_cmpltr_add(i, ASM_CC_TREL, ASM_CT_NZ);
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asm_cmpltr_add(i, ASM_CC_CTYPE, ASM_CT_AND);
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@ -1724,6 +1764,14 @@ asm_normalize(struct asm_inst *i, enum asm_op op)
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asm_cmpltr_add(i, ASM_CC_UNPACK, ASM_CT_L);
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op = ASM_OP_UNPACK4;
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break;
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case ASM_OP_VMSW_0:
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asm_cmpltr_add(i, ASM_CC_VMSW, ASM_CT_0);
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op = ASM_OP_VMSW;
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break;
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case ASM_OP_VMSW_1:
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asm_cmpltr_add(i, ASM_CC_VMSW, ASM_CT_1);
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op = ASM_OP_VMSW;
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break;
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case ASM_OP_XMA_H:
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asm_cmpltr_add(i, ASM_CC_XMA, ASM_CT_H);
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op = ASM_OP_XMA;
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@ -2244,6 +2292,12 @@ asm_extract(enum asm_op op, enum asm_fmt fmt, uint64_t bits,
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operand(i, 1, ASM_OPER_GREG, bits, 6, 7);
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operand(i, 2, ASM_OPER_GREG, bits, 20, 7);
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break;
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case ASM_FMT_I30: /* 2 dst */
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operand(i, 1, ASM_OPER_PREG, bits, 6, 6);
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operand(i, 2, ASM_OPER_PREG, bits, 27, 6);
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op_imm(i, 3, 32LL + FIELD(bits, 14, 5));
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i->i_srcidx++;
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break;
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case ASM_FMT_M1:
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asm_hint(i, ASM_CC_LDHINT);
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operand(i, 1, ASM_OPER_GREG, bits, 6, 7);
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2000-2003 Marcel Moolenaar
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* Copyright (c) 2000-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -67,8 +67,9 @@ static const char *asm_mnemonics[] = {
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"setf", "shl", "shladd", "shladdp4", "shr", "shrp", "srlz", "ssm",
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"st1", "st16", "st2", "st4", "st8", "stf", "stf8", "stfd", "stfe",
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"stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync",
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"tak", "tbit", "thash", "tnat", "tpa", "ttag",
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"tak", "tbit", "tf", "thash", "tnat", "tpa", "ttag",
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"unpack1", "unpack2", "unpack4",
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"vmsw",
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"xchg1", "xchg2", "xchg4", "xchg8", "xma", "xor",
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"zxt1", "zxt2", "zxt4"
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};
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2000-2003 Marcel Moolenaar
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* Copyright (c) 2000-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -206,12 +206,16 @@
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ASM_OP_TBIT_NZ_AND, ASM_OP_TBIT_NZ_OR, ASM_OP_TBIT_NZ_OR_ANDCM, \
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ASM_OP_TBIT_Z, ASM_OP_TBIT_Z_AND, ASM_OP_TBIT_Z_OR, \
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ASM_OP_TBIT_Z_OR_ANDCM, ASM_OP_TBIT_Z_UNC, \
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ASM_OP_TF_NZ_AND, ASM_OP_TF_NZ_OR, ASM_OP_TF_NZ_OR_ANDCM, \
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ASM_OP_TF_Z, ASM_OP_TF_Z_AND, ASM_OP_TF_Z_OR, \
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ASM_OP_TF_Z_OR_ANDCM, ASM_OP_TF_Z_UNC, \
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ASM_OP_TNAT_NZ_AND, ASM_OP_TNAT_NZ_OR, ASM_OP_TNAT_NZ_OR_ANDCM, \
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ASM_OP_TNAT_Z, ASM_OP_TNAT_Z_AND, ASM_OP_TNAT_Z_OR, \
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ASM_OP_TNAT_Z_OR_ANDCM, ASM_OP_TNAT_Z_UNC, \
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ASM_OP_UNPACK1_H, ASM_OP_UNPACK1_L, \
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ASM_OP_UNPACK2_H, ASM_OP_UNPACK2_L, \
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ASM_OP_UNPACK4_H, ASM_OP_UNPACK4_L, \
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ASM_OP_VMSW_0, ASM_OP_VMSW_1, \
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ASM_OP_XMA_H, ASM_OP_XMA_HU, ASM_OP_XMA_L, \
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ASM_OP_NUMBER_OF_OPCODES
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