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Sync specialreg.h changes between amd64 and i386 with few fixes.

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This commit is contained in:
Jung-uk Kim 2006-07-13 16:09:40 +00:00
parent aa00f90024
commit 0758eaa227
2 changed files with 26 additions and 16 deletions
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7
sys/amd64/include/specialreg.h
View File

@ -109,16 +109,18 @@
#define CPUID_SS 0x08000000
#define CPUID_HTT 0x10000000
#define CPUID_TM 0x20000000
#define CPUID_B30 0x40000000
#define CPUID_IA64 0x40000000
#define CPUID_PBE 0x80000000
#define CPUID2_SSE3 0x00000001
#define CPUID2_MON 0x00000008
#define CPUID2_DS_CPL 0x00000010
#define CPUID2_VMX 0x00000020
#define CPUID2_EST 0x00000080
#define CPUID2_TM2 0x00000100
#define CPUID2_CNTXID 0x00000400
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
/*
* Important bits in the AMD extended cpuid flags
@ -190,6 +192,7 @@
#define MSR_THERM_CONTROL 0x19a
#define MSR_THERM_INTERRUPT 0x19b
#define MSR_THERM_STATUS 0x19c
#define MSR_IA32_MISC_ENABLE 0x1a0
#define MSR_DEBUGCTLMSR 0x1d9
#define MSR_LASTBRANCHFROMIP 0x1db
#define MSR_LASTBRANCHTOIP 0x1dc
@ -358,7 +361,7 @@
#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
/* X86-64 MSR's */
/* AMD64 MSR's */
#define MSR_EFER 0xc0000080 /* extended features */
#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */

35
sys/i386/include/specialreg.h
View File

@ -37,12 +37,9 @@
* Bits in 386 special registers:
*/
#define CR0_PE 0x00000001 /* Protected mode Enable */
#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
#define CR0_MP 0x00000002 /* "Math" (fpu) Present */
#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
#ifdef notused
#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
#endif
#define CR0_PG 0x80000000 /* PaGing enable */
/*
@ -107,6 +104,16 @@
#define CPUID_IA64 0x40000000
#define CPUID_PBE 0x80000000
#define CPUID2_SSE3 0x00000001
#define CPUID2_MON 0x00000008
#define CPUID2_DS_CPL 0x00000010
#define CPUID2_VMX 0x00000020
#define CPUID2_EST 0x00000080
#define CPUID2_TM2 0x00000100
#define CPUID2_CNTXID 0x00000400
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
/*
* Important bits in the AMD extended cpuid flags
*/
@ -188,7 +195,7 @@
#define MSR_MTRR64kBase 0x250
#define MSR_MTRR16kBase 0x258
#define MSR_MTRR4kBase 0x268
#define MSR_PAT 0x277
#define MSR_PAT 0x277
#define MSR_MTRRdefType 0x2ff
#define MSR_MC0_CTL 0x400
#define MSR_MC0_STATUS 0x401
@ -202,14 +209,14 @@
#define MSR_MC2_STATUS 0x409
#define MSR_MC2_ADDR 0x40a
#define MSR_MC2_MISC 0x40b
#define MSR_MC4_CTL 0x40c
#define MSR_MC4_STATUS 0x40d
#define MSR_MC4_ADDR 0x40e
#define MSR_MC4_MISC 0x40f
#define MSR_MC3_CTL 0x410
#define MSR_MC3_STATUS 0x411
#define MSR_MC3_ADDR 0x412
#define MSR_MC3_MISC 0x413
#define MSR_MC3_CTL 0x40c
#define MSR_MC3_STATUS 0x40d
#define MSR_MC3_ADDR 0x40e
#define MSR_MC3_MISC 0x40f
#define MSR_MC4_CTL 0x410
#define MSR_MC4_STATUS 0x411
#define MSR_MC4_ADDR 0x412
#define MSR_MC4_MISC 0x413
/*
* Constants related to MSR's.