mlx5fpga: IOCTL for FPGA temperature measurement

Submitted by:   kib@
Approved by:    hselasky (mentor)
MFC after:      1 week
Sponsored by:   Mellanox Technologies
This commit is contained in:
Slava Shwartsman 2018-12-05 14:19:23 +00:00
parent b5f5751275
commit 085b35bb69
8 changed files with 105 additions and 0 deletions

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@ -151,6 +151,7 @@ enum {
MLX5_REG_PMLP = 0x5002,
MLX5_REG_NODE_DESC = 0x6001,
MLX5_REG_HOST_ENDIANNESS = 0x7004,
MLX5_REG_MTMP = 0x900a,
MLX5_REG_MCIA = 0x9014,
MLX5_REG_MPCNT = 0x9051,
};

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@ -60,6 +60,8 @@ struct mlx5_fpga_shell_counters {
int mlx5_fpga_caps(struct mlx5_core_dev *dev);
int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
struct mlx5_fpga_temperature *temp);
int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
void *buf, bool write);

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@ -164,6 +164,38 @@ int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
return 0;
}
int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
struct mlx5_fpga_temperature *temp)
{
u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
int err;
MLX5_SET(mtmp_reg, in, sensor_index, temp->index);
MLX5_SET(mtmp_reg, in, i,
((temp->index < MLX5_FPGA_INTERNAL_SENSORS_LOW) ||
(temp->index > MLX5_FPGA_INTERNAL_SENSORS_HIGH)) ? 1 : 0);
err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
MLX5_REG_MTMP, 0, false);
if (err)
return err;
temp->index = MLX5_GET(mtmp_reg, out, sensor_index);
temp->temperature = MLX5_GET(mtmp_reg, out, temperature);
temp->mte = MLX5_GET(mtmp_reg, out, mte);
temp->max_temperature = MLX5_GET(mtmp_reg, out, max_temperature);
temp->tee = MLX5_GET(mtmp_reg, out, tee);
temp->temperature_threshold_hi = MLX5_GET(mtmp_reg, out,
temperature_threshold_hi);
temp->temperature_threshold_lo = MLX5_GET(mtmp_reg, out,
temperature_threshold_lo);
memcpy(temp->sensor_name, MLX5_ADDR_OF(mtmp_reg, out, sensor_name),
MLX5_FLD_SZ_BYTES(mtmp_reg, sensor_name));
return 0;
}
int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
u32 *fpga_qpn)
{

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@ -442,6 +442,13 @@ int mlx5_fpga_flash_select(struct mlx5_fpga_device *fdev,
}
EXPORT_SYMBOL(mlx5_fpga_flash_select);
int mlx5_fpga_temperature(struct mlx5_fpga_device *fdev,
struct mlx5_fpga_temperature *temp)
{
return mlx5_fpga_query_mtmp(fdev->mdev, temp);
}
EXPORT_SYMBOL(mlx5_fpga_temperature);
struct device *mlx5_fpga_dev(struct mlx5_fpga_device *fdev)
{
return &fdev->mdev->pdev->dev;

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@ -355,6 +355,16 @@ void mlx5_fpga_device_query(struct mlx5_fpga_device *fdev,
*/
struct device *mlx5_fpga_dev(struct mlx5_fpga_device *fdev);
/**
* mlx5_fpga_temperature() - Retrieve FPGA sensor of temperature
* @fdev: The FPGA device
* Return: 0 if successful
* or any other error value otherwise.
*/
int mlx5_fpga_temperature(struct mlx5_fpga_device *fdev,
struct mlx5_fpga_temperature *temp);
/**
* mlx5_fpga_get_cap() - Returns the FPGA cap mailbox from FW without parsing.
* @fdev: The FPGA device

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@ -200,6 +200,7 @@ tools_char_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
struct tools_context *context;
struct mlx5_fpga_device *fdev;
struct mlx5_fpga_query query;
struct mlx5_fpga_temperature *temperature;
u32 fpga_cap[MLX5_ST_SZ_DW(fpga_cap)] = {0};
int arg, err;
@ -254,6 +255,11 @@ tools_char_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
bcopy(&fpga_cap, data, sizeof(fpga_cap));
err = 0;
break;
case MLX5_FPGA_TEMPERATURE:
temperature = (struct mlx5_fpga_temperature *)data;
mlx5_fpga_temperature(fdev, temperature);
err = 0; /* XXXKIB */
break;
default:
dev_err(mlx5_fpga_dev(fdev),
"unknown ioctl command %#08lx\n", cmd);

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@ -8520,6 +8520,31 @@ struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
u8 reserved_0[0x640];
};
struct mlx5_ifc_mtmp_reg_bits {
u8 i[0x1];
u8 reserved_at_1[0x18];
u8 sensor_index[0x7];
u8 reserved_at_20[0x10];
u8 temperature[0x10];
u8 mte[0x1];
u8 mtr[0x1];
u8 reserved_at_42[0x0e];
u8 max_temperature[0x10];
u8 tee[0x2];
u8 reserved_at_62[0x0e];
u8 temperature_threshold_hi[0x10];
u8 reserved_at_80[0x10];
u8 temperature_threshold_lo[0x10];
u8 reserved_at_100[0x20];
u8 sensor_name[0x40];
};
struct mlx5_ifc_lane_2_module_mapping_bits {
u8 reserved_0[0x6];
u8 rx_lane[0x2];

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@ -84,6 +84,12 @@ struct mlx5_fpga_query {
enum mlx5_fpga_status image_status;
};
enum mlx5_fpga_tee {
MLX5_FPGA_TEE_DISABLE = 0,
MLX5_FPGA_TEE_GENERATE_EVENT = 1,
MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
};
/**
* enum mlx5_fpga_access_type - Enumerated the different methods possible for
* accessing the device memory address space
@ -98,6 +104,21 @@ enum mlx5_fpga_access_type {
MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
};
#define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
#define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
struct mlx5_fpga_temperature {
uint32_t temperature;
uint32_t index;
uint32_t tee;
uint32_t max_temperature;
uint32_t temperature_threshold_hi;
uint32_t temperature_threshold_lo;
uint32_t mte;
uint32_t mtr;
char sensor_name[16];
};
#define MLX5_FPGA_CAP_ARR_SZ 0x40
#define MLX5_FPGA_ACCESS_TYPE _IOWINT('m', 0x80)
@ -106,6 +127,7 @@ enum mlx5_fpga_access_type {
#define MLX5_FPGA_IMAGE_SEL _IOWINT('m', 0x83)
#define MLX5_FPGA_QUERY _IOR('m', 0x84, struct mlx5_fpga_query)
#define MLX5_FPGA_CAP _IOR('m', 0x85, u32[MLX5_FPGA_CAP_ARR_SZ])
#define MLX5_FPGA_TEMPERATURE _IOWR('m', 0x86, struct mlx5_fpga_temperature)
#define MLX5_FPGA_TOOLS_NAME_SUFFIX "_mlx5_fpga_tools"