Enable host controller interrupts.

Sponsored by:	DARPA, AFRL
This commit is contained in:
hselasky 2014-05-16 16:36:07 +00:00
parent 3f910b1272
commit 08dac0fb0f
2 changed files with 25 additions and 4 deletions

View File

@ -971,16 +971,20 @@ void
saf1761_otg_interrupt(struct saf1761_otg_softc *sc)
{
uint32_t status;
uint32_t hcstat;
USB_BUS_LOCK(&sc->sc_bus);
status = SAF1761_READ_4(sc, SOTG_DCINTERRUPT);
hcstat = SAF1761_READ_4(sc, SOTG_HCINTERRUPT);
/* acknowledge all host controller interrupts */
SAF1761_WRITE_4(sc, SOTG_HCINTERRUPT, hcstat);
/* acknowledge all interrupts */
status = SAF1761_READ_4(sc, SOTG_DCINTERRUPT);
/* acknowledge all device controller interrupts */
SAF1761_WRITE_4(sc, SOTG_DCINTERRUPT, status);
DPRINTF("DCINTERRUPT=0x%08x SOF=0x%04x\n", status,
SAF1761_READ_2(sc, SOTG_FRAME_NUM));
DPRINTF("DCINTERRUPT=0x%08x HCINTERRUPT=0x%08x SOF=0x%04x\n",
status, hcstat, SAF1761_READ_2(sc, SOTG_FRAME_NUM));
/* update VBUS and ID bits, if any */
if (status & SOTG_DCINTERRUPT_IEVBUS) {
@ -1716,6 +1720,13 @@ saf1761_otg_init(struct saf1761_otg_softc *sc)
/* start the HC */
SAF1761_WRITE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
/* enable HC interrupts */
SAF1761_WRITE_4(sc, SOTG_HCINTERRUPT_ENABLE,
SOTG_HCINTERRUPT_OTG_IRQ |
SOTG_HCINTERRUPT_ISO_IRQ |
SOTG_HCINTERRUPT_ALT_IRQ |
SOTG_HCINTERRUPT_INT_IRQ);
/* poll initial VBUS status */
saf1761_otg_update_vbus(sc);

View File

@ -210,5 +210,15 @@
#define SOTG_USBCMD_LHCR (1 << 7)
#define SOTG_USBCMD_HCRESET (1 << 1)
#define SOTG_USBCMD_RS (1 << 0)
#define SOTG_HCINTERRUPT 0x310
#define SOTG_HCINTERRUPT_OTG_IRQ (1 << 10)
#define SOTG_HCINTERRUPT_ISO_IRQ (1 << 9)
#define SOTG_HCINTERRUPT_ALT_IRQ (1 << 8)
#define SOTG_HCINTERRUPT_INT_IRQ (1 << 7)
#define SOTG_HCINTERRUPT_CLKREADY (1 << 6)
#define SOTG_HCINTERRUPT_HCSUSP (1 << 5)
#define SOTG_HCINTERRUPT_DMAEOTINT (1 << 3)
#define SOTG_HCINTERRUPT_SOFITLINT (1 << 1)
#define SOTG_HCINTERRUPT_ENABLE 0x314
#endif /* _SAF1761_OTG_REG_H_ */