Enable host controller interrupts.
Sponsored by: DARPA, AFRL
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3f910b1272
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@ -971,16 +971,20 @@ void
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saf1761_otg_interrupt(struct saf1761_otg_softc *sc)
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{
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uint32_t status;
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uint32_t hcstat;
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USB_BUS_LOCK(&sc->sc_bus);
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status = SAF1761_READ_4(sc, SOTG_DCINTERRUPT);
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hcstat = SAF1761_READ_4(sc, SOTG_HCINTERRUPT);
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/* acknowledge all host controller interrupts */
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SAF1761_WRITE_4(sc, SOTG_HCINTERRUPT, hcstat);
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/* acknowledge all interrupts */
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status = SAF1761_READ_4(sc, SOTG_DCINTERRUPT);
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/* acknowledge all device controller interrupts */
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SAF1761_WRITE_4(sc, SOTG_DCINTERRUPT, status);
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DPRINTF("DCINTERRUPT=0x%08x SOF=0x%04x\n", status,
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SAF1761_READ_2(sc, SOTG_FRAME_NUM));
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DPRINTF("DCINTERRUPT=0x%08x HCINTERRUPT=0x%08x SOF=0x%04x\n",
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status, hcstat, SAF1761_READ_2(sc, SOTG_FRAME_NUM));
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/* update VBUS and ID bits, if any */
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if (status & SOTG_DCINTERRUPT_IEVBUS) {
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@ -1716,6 +1720,13 @@ saf1761_otg_init(struct saf1761_otg_softc *sc)
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/* start the HC */
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SAF1761_WRITE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
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/* enable HC interrupts */
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SAF1761_WRITE_4(sc, SOTG_HCINTERRUPT_ENABLE,
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SOTG_HCINTERRUPT_OTG_IRQ |
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SOTG_HCINTERRUPT_ISO_IRQ |
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SOTG_HCINTERRUPT_ALT_IRQ |
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SOTG_HCINTERRUPT_INT_IRQ);
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/* poll initial VBUS status */
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saf1761_otg_update_vbus(sc);
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@ -210,5 +210,15 @@
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#define SOTG_USBCMD_LHCR (1 << 7)
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#define SOTG_USBCMD_HCRESET (1 << 1)
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#define SOTG_USBCMD_RS (1 << 0)
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#define SOTG_HCINTERRUPT 0x310
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#define SOTG_HCINTERRUPT_OTG_IRQ (1 << 10)
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#define SOTG_HCINTERRUPT_ISO_IRQ (1 << 9)
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#define SOTG_HCINTERRUPT_ALT_IRQ (1 << 8)
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#define SOTG_HCINTERRUPT_INT_IRQ (1 << 7)
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#define SOTG_HCINTERRUPT_CLKREADY (1 << 6)
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#define SOTG_HCINTERRUPT_HCSUSP (1 << 5)
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#define SOTG_HCINTERRUPT_DMAEOTINT (1 << 3)
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#define SOTG_HCINTERRUPT_SOFITLINT (1 << 1)
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#define SOTG_HCINTERRUPT_ENABLE 0x314
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#endif /* _SAF1761_OTG_REG_H_ */
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