Remove all stuff related to __ARM_ARCH >= 6 from pmap.h header except
for <machine/pmap-v6.h> include. It was used by old pmap-v6 code.
This commit is contained in:
skra
parent
8714daf023
commit
0924d1687c
@ -60,21 +60,10 @@
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/*
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* Pte related macros
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*/
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#if ARM_ARCH_6 || ARM_ARCH_7A
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#ifdef SMP
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#define PTE_NOCACHE 2
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#else
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#define PTE_NOCACHE 1
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#endif
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#define PTE_CACHE 6
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#define PTE_DEVICE 2
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#define PTE_PAGETABLE 6
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#else
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#define PTE_NOCACHE 1
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#define PTE_CACHE 2
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#define PTE_DEVICE PTE_NOCACHE
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#define PTE_PAGETABLE 3
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#endif
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enum mem_type {
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STRONG_ORD = 0,
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@ -104,11 +93,7 @@ enum mem_type {
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#define pmap_page_get_memattr(m) ((m)->md.pv_memattr)
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#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
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#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
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boolean_t pmap_page_is_mapped(vm_page_t);
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#else
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#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
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#endif
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void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
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/*
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@ -131,9 +116,7 @@ struct pv_chunk;
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struct md_page {
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int pvh_attrs;
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vm_memattr_t pv_memattr;
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#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
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vm_offset_t pv_kva; /* first kernel VA mapping */
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#endif
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TAILQ_HEAD(,pv_entry) pv_list;
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};
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@ -164,11 +147,7 @@ struct pmap {
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struct l2_dtable *pm_l2[L2_SIZE];
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cpuset_t pm_active; /* active on cpus */
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struct pmap_statistics pm_stats; /* pmap statictics */
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#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
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TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
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#else
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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#endif
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};
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typedef struct pmap *pmap_t;
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@ -198,10 +177,8 @@ typedef struct pv_entry {
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vm_offset_t pv_va; /* virtual address for mapping */
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TAILQ_ENTRY(pv_entry) pv_list;
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int pv_flags; /* flags (wired, etc...) */
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#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
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pmap_t pv_pmap; /* pmap where mapping lies */
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TAILQ_ENTRY(pv_entry) pv_plist;
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#endif
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} *pv_entry_t;
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/*
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@ -270,9 +247,7 @@ void *pmap_mapdev(vm_offset_t, vm_size_t);
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void pmap_unmapdev(vm_offset_t, vm_size_t);
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vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
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void pmap_debug(int);
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#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
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void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
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#endif
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void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
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vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
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void
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@ -340,119 +315,9 @@ extern int pmap_needs_pte_sync;
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/*
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* User-visible names for the ones that vary with MMU class.
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*/
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#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
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#define L2_AP(x) (L2_AP0(x))
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#else
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#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
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#endif
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#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
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/*
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* AP[2:1] access permissions model:
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*
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* AP[2](APX) - Write Disable
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* AP[1] - User Enable
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* AP[0] - Reference Flag
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*
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* AP[2] AP[1] Kernel User
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* 0 0 R/W N
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* 0 1 R/W R/W
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* 1 0 R N
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* 1 1 R R
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*
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*/
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#define L2_S_PROT_R (0) /* kernel read */
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#define L2_S_PROT_U (L2_AP0(2)) /* user read */
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#define L2_S_REF (L2_AP0(1)) /* reference flag */
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#define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R|L2_APX)
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#define L2_S_EXECUTABLE(pte) (!(pte & L2_XN))
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#define L2_S_WRITABLE(pte) (!(pte & L2_APX))
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#define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF))
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#ifndef SMP
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#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C)
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#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C)
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#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C)
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#else
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#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED)
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#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED)
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#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED)
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#endif /* SMP */
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#define L1_S_PROTO (L1_TYPE_S)
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#define L1_C_PROTO (L1_TYPE_C)
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#define L2_S_PROTO (L2_TYPE_S)
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/*
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* Promotion to a 1MB (SECTION) mapping requires that the corresponding
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* 4KB (SMALL) page mappings have identical settings for the following fields:
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*/
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#define L2_S_PROMOTE (L2_S_REF | L2_SHARED | L2_S_PROT_MASK | \
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L2_XN | L2_S_PROTO)
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/*
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* In order to compare 1MB (SECTION) entry settings with the 4KB (SMALL)
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* page mapping it is necessary to read and shift appropriate bits from
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* L1 entry to positions of the corresponding bits in the L2 entry.
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*/
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#define L1_S_DEMOTE(l1pd) ((((l1pd) & L1_S_PROTO) >> 0) | \
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(((l1pd) & L1_SHARED) >> 6) | \
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(((l1pd) & L1_S_REF) >> 6) | \
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(((l1pd) & L1_S_PROT_MASK) >> 6) | \
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(((l1pd) & L1_S_XN) >> 4))
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#ifndef SMP
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#define ARM_L1S_STRONG_ORD (0)
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#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
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#define ARM_L1S_DEVICE_SHARE (L1_S_B)
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#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1))
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#define ARM_L1S_NRML_IWT_OWT (L1_S_C)
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#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B)
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#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B)
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#define ARM_L2L_STRONG_ORD (0)
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#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
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#define ARM_L2L_DEVICE_SHARE (L2_B)
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#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1))
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#define ARM_L2L_NRML_IWT_OWT (L2_C)
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#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B)
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#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B)
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#define ARM_L2S_STRONG_ORD (0)
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#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
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#define ARM_L2S_DEVICE_SHARE (L2_B)
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#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1))
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#define ARM_L2S_NRML_IWT_OWT (L2_C)
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#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B)
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#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B)
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#else
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#define ARM_L1S_STRONG_ORD (0)
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#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
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#define ARM_L1S_DEVICE_SHARE (L1_S_B)
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#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
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#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
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#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
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#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
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#define ARM_L2L_STRONG_ORD (0)
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#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
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#define ARM_L2L_DEVICE_SHARE (L2_B)
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#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
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#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
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#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
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#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
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#define ARM_L2S_STRONG_ORD (0)
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#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
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#define ARM_L2S_DEVICE_SHARE (L2_B)
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#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
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#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
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#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
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#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
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#endif /* SMP */
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#elif ARM_NMMUS > 1
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#if ARM_NMMUS > 1
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/* More than one MMU class configured; use variables. */
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#define L2_S_PROT_U pte_l2_s_prot_u
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#define L2_S_PROT_W pte_l2_s_prot_w
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@ -494,7 +359,7 @@ extern int pmap_needs_pte_sync;
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#endif /* ARM_NMMUS > 1 */
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#if defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A
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#if defined(CPU_XSCALE_81342)
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#define PMAP_NEEDS_PTE_SYNC 1
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#define PMAP_INCLUDE_PTE_SYNC
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#else
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@ -505,8 +370,6 @@ extern int pmap_needs_pte_sync;
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* These macros return various bits based on kernel/user and protection.
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* Note that the compiler will usually fold these at compile time.
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*/
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#if (ARM_MMU_V6 + ARM_MMU_V7) == 0
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#define L1_S_PROT_U (L1_S_AP(AP_U))
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#define L1_S_PROT_W (L1_S_AP(AP_W))
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#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
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@ -524,27 +387,6 @@ extern int pmap_needs_pte_sync;
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#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
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#else
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#define L1_S_PROT_U (L1_S_AP(AP_U))
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#define L1_S_PROT_W (L1_S_APX) /* Write disable */
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#define L1_S_PROT_MASK (L1_S_PROT_W|L1_S_PROT_U)
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#define L1_S_REF (L1_S_AP(AP_REF)) /* Reference flag */
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#define L1_S_WRITABLE(pd) (!((pd) & L1_S_PROT_W))
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#define L1_S_EXECUTABLE(pd) (!((pd) & L1_S_XN))
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#define L1_S_REFERENCED(pd) ((pd) & L1_S_REF)
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#define L1_S_PROT(ku, pr) (((((ku) == PTE_KERNEL) ? 0 : L1_S_PROT_U) | \
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(((pr) & VM_PROT_WRITE) ? 0 : L1_S_PROT_W) | \
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(((pr) & VM_PROT_EXECUTE) ? 0 : L1_S_XN)))
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#define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3))
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#define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
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#define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
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#endif
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/*
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* Macros to test if a mapping is mappable with an L1 Section mapping
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@ -619,12 +461,12 @@ extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
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vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
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extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
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#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 || defined(CPU_XSCALE_81342)
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#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_81342)
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void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
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void pmap_zero_page_generic(vm_paddr_t, int, int);
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void pmap_pte_init_generic(void);
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#endif /* (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 */
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#endif /* ARM_MMU_GENERIC != 0 */
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#if ARM_MMU_XSCALE == 1
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void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
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