Follow exactly the steps in architecture manual for correctly invalidating
TLB entries instead of trying to cut corners.
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6a7d71b6f3
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@ -425,9 +425,9 @@ tlbie(vm_offset_t va)
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{
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mtx_lock_spin(&tlbie_mtx);
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__asm __volatile("ptesync");
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__asm __volatile("tlbie %0" :: "r"(va));
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__asm __volatile("tlbsync");
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powerpc_sync();
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__asm __volatile("eieio; tlbsync; ptesync");
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mtx_unlock_spin(&tlbie_mtx);
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}
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@ -211,14 +211,14 @@ TLBIE(uint64_t vpn) {
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mfmsr %0; \
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mr %1, %0; \
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insrdi %1,%5,1,0; \
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mtmsrd %1; \
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mtmsrd %1; isync; \
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ptesync; \
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\
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sld %1,%2,%4; \
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or %1,%1,%3; \
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tlbie %1; \
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\
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mtmsrd %0; \
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mtmsrd %0; isync; \
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eieio; \
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tlbsync; \
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ptesync;"
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