Various fixes to make stack traces using the unwind tables work properly.
This commit is contained in:
dfr
parent
439a7ddc5f
commit
09a1f139c4
@ -58,6 +58,9 @@
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mov out1=r14; \
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mov out2=sp;; \
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add sp=-16,sp;; \
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.prologue; \
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.save rp,r0; \
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.body; \
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br.call.sptk.few rp=trap; \
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3: br.sptk.many exception_restore
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@ -74,11 +77,13 @@ ia64_vector_table:
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/* 0x0000: VHPT Translation vector */
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interruption_VHPT_Translation:
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TRAP(0)
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.align 1024
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/* 0x0400: Instruction TLB vector */
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interruption_Instruction_TLB:
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mov r16=cr.ifa
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mov r17=pr
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;;
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@ -157,6 +162,7 @@ ia64_vector_table:
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/* 0x0800: Data TLB vector */
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interruption_Data_TLB:
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mov r16=cr.ifa
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mov r17=pr
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;;
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@ -235,6 +241,7 @@ ia64_vector_table:
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/* 0x0c00: Alternate Instruction TLB vector */
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interruption_Alternate_Instruction_TLB:
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mov r16=cr.ifa // where did it happen
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;;
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mov r18=pr // save predicates
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@ -259,6 +266,7 @@ ia64_vector_table:
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/* 0x1000: Alternate Data TLB vector */
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interruption_Alternate_Data_TLB:
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mov r16=cr.ifa // where did it happen
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mov r18=pr // save predicates
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;;
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@ -282,21 +290,25 @@ ia64_vector_table:
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/* 0x1400: Data Nested TLB vector */
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interruption_Data_Nested_TLB:
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TRAP(5)
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.align 1024
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/* 0x1800: Instruction Key Miss vector */
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interruption_Instruction_Key_Miss:
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TRAP(6)
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.align 1024
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/* 0x1c00: Data Key Miss vector */
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interruption_Data_Key_Miss:
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TRAP(7)
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.align 1024
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/* 0x2000: Dirty-Bit vector */
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interruption_Dirty_Bit:
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mov r16=cr.ifa
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mov r17=pr
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mov r20=PAGE_SHIFT<<2 // XXX get page size from VHPT
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@ -367,6 +379,7 @@ ia64_vector_table:
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/* 0x2400: Instruction Access-Bit vector */
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interruption_Instruction_Access_Bit:
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mov r16=cr.ifa
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mov r17=pr
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mov r20=PAGE_SHIFT<<2 // XXX get page size from VHPT
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@ -437,6 +450,7 @@ ia64_vector_table:
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/* 0x2800: Data Access-Bit vector */
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interruption_Data_Access_Bit:
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mov r16=cr.ifa
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mov r17=pr
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mov r20=PAGE_SHIFT<<2 // XXX get page size from VHPT
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@ -507,6 +521,7 @@ ia64_vector_table:
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/* 0x2c00: Break Instruction vector */
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interruption_Break:
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mov r16=pr // save pr for a moment
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mov r17=cr.iim;; // read break value
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mov r18=0x100000;; // syscall number
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@ -529,6 +544,7 @@ ia64_vector_table:
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/* 0x3000: External Interrupt vector */
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interruption_External_Interrupt:
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mov r16=b0 // save user's b0
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1: mov r17=ip;; // construct return address
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add r17=2f-1b,r17;; // for exception_save
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@ -564,276 +580,331 @@ ia64_vector_table:
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/* 0x3400: Reserved */
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interruption_3400:
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TRAP(13)
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.align 1024
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/* 0x3800: Reserved */
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interruption_3800:
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TRAP(14)
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.align 1024
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/* 0x3c00: Reserved */
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interruption_3c00:
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TRAP(15)
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.align 1024
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/* 0x4000: Reserved */
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interruption_4000:
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TRAP(16)
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.align 1024
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/* 0x4400: Reserved */
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interruption_4400:
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TRAP(17)
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.align 1024
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/* 0x4800: Reserved */
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interruption_4800:
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TRAP(18)
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.align 1024
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/* 0x4c00: Reserved */
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interruption_4c00:
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TRAP(19)
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.align 1024
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/* 0x5000: Page Not Present vector */
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interruption_Page_Not_Present:
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TRAP(20)
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.align 256
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/* 0x5100: Key Permission vector */
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interruption_Key_Permission:
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TRAP(21)
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.align 256
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/* 0x5200: Instruction Access Rights vector */
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interruption_Instruction_Access_Rights:
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TRAP(22)
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.align 256
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/* 0x5300: Data Access Rights vector */
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interruption_Data_Access_Rights:
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TRAP(23)
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.align 256
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/* 0x5400: General Exception vector */
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interruption_General_Exception:
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TRAP(24)
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.align 256
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/* 0x5500: Disabled FP-Register vector */
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interruption_Disabled_FP_Register:
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TRAP(25)
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.align 256
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/* 0x5600: NaT Consumption vector */
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interruption_NaT_Consumption:
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TRAP(26)
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.align 256
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/* 0x5700: Speculation vector */
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interruption_Speculation:
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TRAP(27)
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.align 256
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/* 0x5800: Reserved */
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interruption_5800:
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TRAP(28)
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.align 256
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/* 0x5900: Debug vector */
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interruption_Debug:
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TRAP(29)
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.align 256
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/* 0x5a00: Unaligned Reference vector */
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interruption_Unaligned_Reference:
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TRAP(30)
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.align 256
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/* 0x5b00: Unsupported Data Reference vector */
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interruption_Unsupported_Data_Reference:
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TRAP(31)
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.align 256
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/* 0x5c00: Floating-point Fault vector */
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interruption_Floating_Point_Fault:
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TRAP(32)
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.align 256
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/* 0x5d00: Floating-point Trap vector */
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interruption_Floating_Point_Trap:
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TRAP(33)
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.align 256
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/* 0x5e00: Lower-Privilege Transfer Trap vector */
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interruption_Lower_Privilege_Transfer_Trap:
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TRAP(34)
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.align 256
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/* 0x5f00: Taken Branch Trap vector */
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interruption_Taken_Branch_Trap:
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TRAP(35)
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.align 256
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/* 0x6000: Single Step Trap vector */
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interruption_Single_Step_Trap:
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TRAP(36)
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.align 256
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/* 0x6100: Reserved */
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interruption_6100:
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TRAP(37)
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.align 256
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/* 0x6200: Reserved */
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interruption_6200:
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TRAP(38)
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.align 256
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/* 0x6300: Reserved */
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interruption_6300:
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TRAP(39)
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.align 256
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/* 0x6400: Reserved */
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interruption_6400:
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TRAP(40)
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.align 256
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/* 0x6500: Reserved */
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interruption_6500:
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TRAP(41)
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.align 256
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/* 0x6600: Reserved */
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interruption_6600:
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TRAP(42)
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.align 256
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/* 0x6700: Reserved */
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interruption_6700:
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TRAP(43)
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.align 256
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/* 0x6800: Reserved */
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interruption_6800:
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TRAP(44)
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.align 256
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/* 0x6900: IA-32 Exception vector */
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interruption_IA_32_Exception:
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TRAP(45)
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.align 256
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/* 0x6a00: IA-32 Intercept vector */
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interruption_IA_32_Intercept:
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TRAP(46)
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.align 256
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/* 0x6b00: IA-32 Interrupt vector */
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interruption_IA_32_Interrupt:
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TRAP(47)
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.align 256
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/* 0x6c00: Reserved */
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interruption_6c00:
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TRAP(48)
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.align 256
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/* 0x6d00: Reserved */
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interruption_6d00:
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TRAP(49)
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.align 256
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/* 0x6e00: Reserved */
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interruption_6e00:
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TRAP(50)
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.align 256
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/* 0x6f00: Reserved */
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interruption_6f00:
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TRAP(51)
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.align 256
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/* 0x7000: Reserved */
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interruption_7000:
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TRAP(52)
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.align 256
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/* 0x7100: Reserved */
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interruption_7100:
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TRAP(53)
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.align 256
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/* 0x7200: Reserved */
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interruption_7200:
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TRAP(54)
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.align 256
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/* 0x7300: Reserved */
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interruption_7300:
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TRAP(55)
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.align 256
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/* 0x7400: Reserved */
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interruption_7400:
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TRAP(56)
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.align 256
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/* 0x7500: Reserved */
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interruption_7500:
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TRAP(57)
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.align 256
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/* 0x7600: Reserved */
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interruption_7600:
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TRAP(58)
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.align 256
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/* 0x7700: Reserved */
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interruption_7700:
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TRAP(59)
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.align 256
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/* 0x7800: Reserved */
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interruption_7800:
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TRAP(60)
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.align 256
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/* 0x7900: Reserved */
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interruption_7900:
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TRAP(61)
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.align 256
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/* 0x7a00: Reserved */
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interruption_7a00:
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TRAP(62)
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.align 256
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/* 0x7b00: Reserved */
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interruption_7b00:
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TRAP(63)
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.align 256
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/* 0x7c00: Reserved */
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interruption_7c00:
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TRAP(64)
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.align 256
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/* 0x7d00: Reserved */
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interruption_7d00:
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TRAP(65)
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.align 256
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/* 0x7e00: Reserved */
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interruption_7e00:
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TRAP(66)
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.align 256
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/* 0x7f00: Reserved */
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interruption_7f00:
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TRAP(67)
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.align 256
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@ -1253,6 +1324,9 @@ END(exception_save)
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* r16 saved predicates
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*/
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ENTRY(do_syscall, 0)
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.prologue
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.save rp,r0
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.body
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rsm psr.dt // physical addressing for a moment
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mov r17=sp;; // save user sp
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srlz.d // serialize psr.dt
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@ -1499,5 +1573,7 @@ Lsaveargs:
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;;
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st8 [r31]=r39
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br.ret.sptk.many b0
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.global do_syscall_end
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do_syscall_end:
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END(do_syscall)
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@ -58,6 +58,9 @@
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mov out1=r14; \
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mov out2=sp;; \
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add sp=-16,sp;; \
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.prologue; \
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.save rp,r0; \
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.body; \
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br.call.sptk.few rp=trap; \
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3: br.sptk.many exception_restore
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@ -74,11 +77,13 @@ ia64_vector_table:
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/* 0x0000: VHPT Translation vector */
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||||
|
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interruption_VHPT_Translation:
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TRAP(0)
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.align 1024
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/* 0x0400: Instruction TLB vector */
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|
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interruption_Instruction_TLB:
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mov r16=cr.ifa
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mov r17=pr
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;;
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@ -157,6 +162,7 @@ ia64_vector_table:
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/* 0x0800: Data TLB vector */
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interruption_Data_TLB:
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mov r16=cr.ifa
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mov r17=pr
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;;
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@ -235,6 +241,7 @@ ia64_vector_table:
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/* 0x0c00: Alternate Instruction TLB vector */
|
||||
|
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interruption_Alternate_Instruction_TLB:
|
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mov r16=cr.ifa // where did it happen
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;;
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mov r18=pr // save predicates
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@ -259,6 +266,7 @@ ia64_vector_table:
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/* 0x1000: Alternate Data TLB vector */
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||||
|
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interruption_Alternate_Data_TLB:
|
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mov r16=cr.ifa // where did it happen
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mov r18=pr // save predicates
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;;
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@ -282,21 +290,25 @@ ia64_vector_table:
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/* 0x1400: Data Nested TLB vector */
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interruption_Data_Nested_TLB:
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TRAP(5)
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.align 1024
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/* 0x1800: Instruction Key Miss vector */
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interruption_Instruction_Key_Miss:
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TRAP(6)
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.align 1024
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/* 0x1c00: Data Key Miss vector */
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interruption_Data_Key_Miss:
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TRAP(7)
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.align 1024
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/* 0x2000: Dirty-Bit vector */
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|
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interruption_Dirty_Bit:
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mov r16=cr.ifa
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mov r17=pr
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mov r20=PAGE_SHIFT<<2 // XXX get page size from VHPT
|
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@ -367,6 +379,7 @@ ia64_vector_table:
|
||||
|
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/* 0x2400: Instruction Access-Bit vector */
|
||||
|
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interruption_Instruction_Access_Bit:
|
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mov r16=cr.ifa
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mov r17=pr
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mov r20=PAGE_SHIFT<<2 // XXX get page size from VHPT
|
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@ -437,6 +450,7 @@ ia64_vector_table:
|
||||
|
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/* 0x2800: Data Access-Bit vector */
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|
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interruption_Data_Access_Bit:
|
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mov r16=cr.ifa
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mov r17=pr
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mov r20=PAGE_SHIFT<<2 // XXX get page size from VHPT
|
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@ -507,6 +521,7 @@ ia64_vector_table:
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/* 0x2c00: Break Instruction vector */
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interruption_Break:
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mov r16=pr // save pr for a moment
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mov r17=cr.iim;; // read break value
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mov r18=0x100000;; // syscall number
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@ -529,6 +544,7 @@ ia64_vector_table:
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||||
|
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/* 0x3000: External Interrupt vector */
|
||||
|
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interruption_External_Interrupt:
|
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mov r16=b0 // save user's b0
|
||||
1: mov r17=ip;; // construct return address
|
||||
add r17=2f-1b,r17;; // for exception_save
|
||||
@ -564,276 +580,331 @@ ia64_vector_table:
|
||||
|
||||
/* 0x3400: Reserved */
|
||||
|
||||
interruption_3400:
|
||||
TRAP(13)
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.align 1024
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||||
|
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/* 0x3800: Reserved */
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||||
|
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interruption_3800:
|
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TRAP(14)
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.align 1024
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|
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/* 0x3c00: Reserved */
|
||||
|
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interruption_3c00:
|
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TRAP(15)
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.align 1024
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/* 0x4000: Reserved */
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interruption_4000:
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TRAP(16)
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.align 1024
|
||||
|
||||
/* 0x4400: Reserved */
|
||||
|
||||
interruption_4400:
|
||||
TRAP(17)
|
||||
.align 1024
|
||||
|
||||
/* 0x4800: Reserved */
|
||||
|
||||
interruption_4800:
|
||||
TRAP(18)
|
||||
.align 1024
|
||||
|
||||
/* 0x4c00: Reserved */
|
||||
|
||||
interruption_4c00:
|
||||
TRAP(19)
|
||||
.align 1024
|
||||
|
||||
/* 0x5000: Page Not Present vector */
|
||||
|
||||
interruption_Page_Not_Present:
|
||||
TRAP(20)
|
||||
.align 256
|
||||
|
||||
/* 0x5100: Key Permission vector */
|
||||
|
||||
interruption_Key_Permission:
|
||||
TRAP(21)
|
||||
.align 256
|
||||
|
||||
/* 0x5200: Instruction Access Rights vector */
|
||||
|
||||
interruption_Instruction_Access_Rights:
|
||||
TRAP(22)
|
||||
.align 256
|
||||
|
||||
/* 0x5300: Data Access Rights vector */
|
||||
|
||||
interruption_Data_Access_Rights:
|
||||
TRAP(23)
|
||||
.align 256
|
||||
|
||||
/* 0x5400: General Exception vector */
|
||||
|
||||
interruption_General_Exception:
|
||||
TRAP(24)
|
||||
.align 256
|
||||
|
||||
/* 0x5500: Disabled FP-Register vector */
|
||||
|
||||
interruption_Disabled_FP_Register:
|
||||
TRAP(25)
|
||||
.align 256
|
||||
|
||||
/* 0x5600: NaT Consumption vector */
|
||||
|
||||
interruption_NaT_Consumption:
|
||||
TRAP(26)
|
||||
.align 256
|
||||
|
||||
/* 0x5700: Speculation vector */
|
||||
|
||||
interruption_Speculation:
|
||||
TRAP(27)
|
||||
.align 256
|
||||
|
||||
/* 0x5800: Reserved */
|
||||
|
||||
interruption_5800:
|
||||
TRAP(28)
|
||||
.align 256
|
||||
|
||||
/* 0x5900: Debug vector */
|
||||
|
||||
interruption_Debug:
|
||||
TRAP(29)
|
||||
.align 256
|
||||
|
||||
/* 0x5a00: Unaligned Reference vector */
|
||||
|
||||
interruption_Unaligned_Reference:
|
||||
TRAP(30)
|
||||
.align 256
|
||||
|
||||
/* 0x5b00: Unsupported Data Reference vector */
|
||||
|
||||
interruption_Unsupported_Data_Reference:
|
||||
TRAP(31)
|
||||
.align 256
|
||||
|
||||
/* 0x5c00: Floating-point Fault vector */
|
||||
|
||||
interruption_Floating_Point_Fault:
|
||||
TRAP(32)
|
||||
.align 256
|
||||
|
||||
/* 0x5d00: Floating-point Trap vector */
|
||||
|
||||
interruption_Floating_Point_Trap:
|
||||
TRAP(33)
|
||||
.align 256
|
||||
|
||||
/* 0x5e00: Lower-Privilege Transfer Trap vector */
|
||||
|
||||
interruption_Lower_Privilege_Transfer_Trap:
|
||||
TRAP(34)
|
||||
.align 256
|
||||
|
||||
/* 0x5f00: Taken Branch Trap vector */
|
||||
|
||||
interruption_Taken_Branch_Trap:
|
||||
TRAP(35)
|
||||
.align 256
|
||||
|
||||
/* 0x6000: Single Step Trap vector */
|
||||
|
||||
interruption_Single_Step_Trap:
|
||||
TRAP(36)
|
||||
.align 256
|
||||
|
||||
/* 0x6100: Reserved */
|
||||
|
||||
interruption_6100:
|
||||
TRAP(37)
|
||||
.align 256
|
||||
|
||||
/* 0x6200: Reserved */
|
||||
|
||||
interruption_6200:
|
||||
TRAP(38)
|
||||
.align 256
|
||||
|
||||
/* 0x6300: Reserved */
|
||||
|
||||
interruption_6300:
|
||||
TRAP(39)
|
||||
.align 256
|
||||
|
||||
/* 0x6400: Reserved */
|
||||
|
||||
interruption_6400:
|
||||
TRAP(40)
|
||||
.align 256
|
||||
|
||||
/* 0x6500: Reserved */
|
||||
|
||||
interruption_6500:
|
||||
TRAP(41)
|
||||
.align 256
|
||||
|
||||
/* 0x6600: Reserved */
|
||||
|
||||
interruption_6600:
|
||||
TRAP(42)
|
||||
.align 256
|
||||
|
||||
/* 0x6700: Reserved */
|
||||
|
||||
interruption_6700:
|
||||
TRAP(43)
|
||||
.align 256
|
||||
|
||||
/* 0x6800: Reserved */
|
||||
|
||||
interruption_6800:
|
||||
TRAP(44)
|
||||
.align 256
|
||||
|
||||
/* 0x6900: IA-32 Exception vector */
|
||||
|
||||
interruption_IA_32_Exception:
|
||||
TRAP(45)
|
||||
.align 256
|
||||
|
||||
/* 0x6a00: IA-32 Intercept vector */
|
||||
|
||||
interruption_IA_32_Intercept:
|
||||
TRAP(46)
|
||||
.align 256
|
||||
|
||||
/* 0x6b00: IA-32 Interrupt vector */
|
||||
|
||||
interruption_IA_32_Interrupt:
|
||||
TRAP(47)
|
||||
.align 256
|
||||
|
||||
/* 0x6c00: Reserved */
|
||||
|
||||
interruption_6c00:
|
||||
TRAP(48)
|
||||
.align 256
|
||||
|
||||
/* 0x6d00: Reserved */
|
||||
|
||||
interruption_6d00:
|
||||
TRAP(49)
|
||||
.align 256
|
||||
|
||||
/* 0x6e00: Reserved */
|
||||
|
||||
interruption_6e00:
|
||||
TRAP(50)
|
||||
.align 256
|
||||
|
||||
/* 0x6f00: Reserved */
|
||||
|
||||
interruption_6f00:
|
||||
TRAP(51)
|
||||
.align 256
|
||||
|
||||
/* 0x7000: Reserved */
|
||||
|
||||
interruption_7000:
|
||||
TRAP(52)
|
||||
.align 256
|
||||
|
||||
/* 0x7100: Reserved */
|
||||
|
||||
interruption_7100:
|
||||
TRAP(53)
|
||||
.align 256
|
||||
|
||||
/* 0x7200: Reserved */
|
||||
|
||||
interruption_7200:
|
||||
TRAP(54)
|
||||
.align 256
|
||||
|
||||
/* 0x7300: Reserved */
|
||||
|
||||
interruption_7300:
|
||||
TRAP(55)
|
||||
.align 256
|
||||
|
||||
/* 0x7400: Reserved */
|
||||
|
||||
interruption_7400:
|
||||
TRAP(56)
|
||||
.align 256
|
||||
|
||||
/* 0x7500: Reserved */
|
||||
|
||||
interruption_7500:
|
||||
TRAP(57)
|
||||
.align 256
|
||||
|
||||
/* 0x7600: Reserved */
|
||||
|
||||
interruption_7600:
|
||||
TRAP(58)
|
||||
.align 256
|
||||
|
||||
/* 0x7700: Reserved */
|
||||
|
||||
interruption_7700:
|
||||
TRAP(59)
|
||||
.align 256
|
||||
|
||||
/* 0x7800: Reserved */
|
||||
|
||||
interruption_7800:
|
||||
TRAP(60)
|
||||
.align 256
|
||||
|
||||
/* 0x7900: Reserved */
|
||||
|
||||
interruption_7900:
|
||||
TRAP(61)
|
||||
.align 256
|
||||
|
||||
/* 0x7a00: Reserved */
|
||||
|
||||
interruption_7a00:
|
||||
TRAP(62)
|
||||
.align 256
|
||||
|
||||
/* 0x7b00: Reserved */
|
||||
|
||||
interruption_7b00:
|
||||
TRAP(63)
|
||||
.align 256
|
||||
|
||||
/* 0x7c00: Reserved */
|
||||
|
||||
interruption_7c00:
|
||||
TRAP(64)
|
||||
.align 256
|
||||
|
||||
/* 0x7d00: Reserved */
|
||||
|
||||
interruption_7d00:
|
||||
TRAP(65)
|
||||
.align 256
|
||||
|
||||
/* 0x7e00: Reserved */
|
||||
|
||||
interruption_7e00:
|
||||
TRAP(66)
|
||||
.align 256
|
||||
|
||||
/* 0x7f00: Reserved */
|
||||
|
||||
interruption_7f00:
|
||||
TRAP(67)
|
||||
.align 256
|
||||
|
||||
@ -1253,6 +1324,9 @@ END(exception_save)
|
||||
* r16 saved predicates
|
||||
*/
|
||||
ENTRY(do_syscall, 0)
|
||||
.prologue
|
||||
.save rp,r0
|
||||
.body
|
||||
rsm psr.dt // physical addressing for a moment
|
||||
mov r17=sp;; // save user sp
|
||||
srlz.d // serialize psr.dt
|
||||
@ -1499,5 +1573,7 @@ Lsaveargs:
|
||||
;;
|
||||
st8 [r31]=r39
|
||||
br.ret.sptk.many b0
|
||||
.global do_syscall_end
|
||||
do_syscall_end:
|
||||
|
||||
END(do_syscall)
|
||||
|
||||
@ -119,8 +119,8 @@ ENTRY(__start, 1)
|
||||
;;
|
||||
ld8 out0=[out0]
|
||||
;;
|
||||
add r16=PCB_B0,out0 // return to mi_startup
|
||||
movl r17=mi_startup
|
||||
add r16=PCB_B0,out0 // return to mi_startup_trampoline
|
||||
movl r17=mi_startup_trampoline
|
||||
;;
|
||||
st8 [r16]=r17
|
||||
;;
|
||||
@ -130,6 +130,19 @@ ENTRY(__start, 1)
|
||||
|
||||
END(__start)
|
||||
|
||||
|
||||
ENTRY(mi_startup_trampoline, 0)
|
||||
.prologue
|
||||
.save rp,r0
|
||||
.body
|
||||
|
||||
br.call.sptk.many rp=mi_startup
|
||||
|
||||
// Should never happen
|
||||
1: br.cond.sptk.few 1b
|
||||
|
||||
END(mi_startup_trampoline)
|
||||
|
||||
/*
|
||||
* AP wake-up entry point. The handoff state is similar as for the BSP,
|
||||
* as described on page 3-9 of the IPF SAL Specification. The difference
|
||||
|
||||
@ -119,8 +119,8 @@ ENTRY(__start, 1)
|
||||
;;
|
||||
ld8 out0=[out0]
|
||||
;;
|
||||
add r16=PCB_B0,out0 // return to mi_startup
|
||||
movl r17=mi_startup
|
||||
add r16=PCB_B0,out0 // return to mi_startup_trampoline
|
||||
movl r17=mi_startup_trampoline
|
||||
;;
|
||||
st8 [r16]=r17
|
||||
;;
|
||||
@ -130,6 +130,19 @@ ENTRY(__start, 1)
|
||||
|
||||
END(__start)
|
||||
|
||||
|
||||
ENTRY(mi_startup_trampoline, 0)
|
||||
.prologue
|
||||
.save rp,r0
|
||||
.body
|
||||
|
||||
br.call.sptk.many rp=mi_startup
|
||||
|
||||
// Should never happen
|
||||
1: br.cond.sptk.few 1b
|
||||
|
||||
END(mi_startup_trampoline)
|
||||
|
||||
/*
|
||||
* AP wake-up entry point. The handoff state is similar as for the BSP,
|
||||
* as described on page 3-9 of the IPF SAL Specification. The difference
|
||||
|
||||
@ -149,10 +149,15 @@ END(ia64_physical_mode)
|
||||
*/
|
||||
ENTRY(ia64_call_efi_physical, 6)
|
||||
|
||||
.prologue
|
||||
.regstk 6,4,5,0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,6,4,5,0
|
||||
;;
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
;;
|
||||
.body
|
||||
br.call.sptk.many rp=ia64_physical_mode
|
||||
;;
|
||||
mov loc2=r8 // psr to restore mode
|
||||
@ -357,8 +362,13 @@ ENTRY(copystr, 4)
|
||||
END(copystr)
|
||||
|
||||
ENTRY(copyinstr, 4)
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that src addr
|
||||
;;
|
||||
@ -392,8 +402,13 @@ ENTRY(copyinstr, 4)
|
||||
END(copyinstr)
|
||||
|
||||
ENTRY(copyoutstr, 4)
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that dest addr
|
||||
;;
|
||||
@ -507,8 +522,13 @@ END(memcpy)
|
||||
|
||||
ENTRY(copyin, 3)
|
||||
|
||||
alloc loc0=ar.pfs,3,3,3,0
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that src addr
|
||||
;;
|
||||
@ -542,8 +562,13 @@ END(copyin)
|
||||
|
||||
ENTRY(copyout, 3)
|
||||
|
||||
alloc loc0=ar.pfs,3,3,3,0
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that dest addr
|
||||
;;
|
||||
|
||||
@ -149,10 +149,15 @@ END(ia64_physical_mode)
|
||||
*/
|
||||
ENTRY(ia64_call_efi_physical, 6)
|
||||
|
||||
.prologue
|
||||
.regstk 6,4,5,0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,6,4,5,0
|
||||
;;
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
;;
|
||||
.body
|
||||
br.call.sptk.many rp=ia64_physical_mode
|
||||
;;
|
||||
mov loc2=r8 // psr to restore mode
|
||||
@ -357,8 +362,13 @@ ENTRY(copystr, 4)
|
||||
END(copystr)
|
||||
|
||||
ENTRY(copyinstr, 4)
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that src addr
|
||||
;;
|
||||
@ -392,8 +402,13 @@ ENTRY(copyinstr, 4)
|
||||
END(copyinstr)
|
||||
|
||||
ENTRY(copyoutstr, 4)
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that dest addr
|
||||
;;
|
||||
@ -507,8 +522,13 @@ END(memcpy)
|
||||
|
||||
ENTRY(copyin, 3)
|
||||
|
||||
alloc loc0=ar.pfs,3,3,3,0
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that src addr
|
||||
;;
|
||||
@ -542,8 +562,13 @@ END(copyin)
|
||||
|
||||
ENTRY(copyout, 3)
|
||||
|
||||
alloc loc0=ar.pfs,3,3,3,0
|
||||
.prologue
|
||||
.regstk 4, 3, 4, 0
|
||||
.save ar.pfs,loc0
|
||||
alloc loc0=ar.pfs,4,3,4,0
|
||||
.save rp,loc1
|
||||
mov loc1=rp
|
||||
.body
|
||||
|
||||
movl loc2=VM_MAXUSER_ADDRESS // make sure that dest addr
|
||||
;;
|
||||
|
||||
@ -625,6 +625,9 @@ END(restorehighfp)
|
||||
* fork_exit() is in r5, and the argument is in r6.
|
||||
*/
|
||||
ENTRY(fork_trampoline, 0)
|
||||
.prologue
|
||||
.save rp,r0
|
||||
.body
|
||||
alloc r14=ar.pfs,0,0,3,0
|
||||
;;
|
||||
mov b0=r5
|
||||
@ -632,7 +635,8 @@ ENTRY(fork_trampoline, 0)
|
||||
mov out1=r6
|
||||
add out2=16,sp
|
||||
;;
|
||||
br.call.sptk.few b6=fork_exit
|
||||
br.call.sptk.few rp=fork_exit
|
||||
;;
|
||||
br.cond.sptk.many exception_restore
|
||||
|
||||
END(fork_trampoline)
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user