- Correct bus space resource type for register access.
- Add configuration of interrupt type and polarity via FDT. Sponsored by: DARPA, AFRL
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6712d8d387
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0a93966003
@ -2052,7 +2052,8 @@ saf1761_otg_init(struct saf1761_otg_softc *sc)
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SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG,
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SOTG_INTERRUPT_CFG_CDBGMOD |
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SOTG_INTERRUPT_CFG_DDBGMODIN |
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SOTG_INTERRUPT_CFG_DDBGMODOUT);
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SOTG_INTERRUPT_CFG_DDBGMODOUT |
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sc->sc_interrupt_cfg);
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/* enable VBUS and ID interrupt */
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SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
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@ -144,6 +144,7 @@ struct saf1761_otg_softc {
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uint32_t sc_host_isoc_map;
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uint32_t sc_intr_enable; /* enabled interrupts */
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uint32_t sc_hw_mode; /* hardware mode */
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uint32_t sc_interrupt_cfg; /* interrupt configuration */
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uint32_t sc_bounce_buffer[1024 / 4];
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@ -156,6 +156,18 @@ saf1761_otg_fdt_attach(device_t dev)
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_DREQ_POL;
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}
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/* get IRQ polarity */
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if (OF_getprop(ofw_bus_get_node(dev), "int-polarity",
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¶m, sizeof(param)) > 0) {
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sc->sc_interrupt_cfg |= SOTG_INTERRUPT_CFG_INTPOL;
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}
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/* get IRQ level triggering */
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if (OF_getprop(ofw_bus_get_node(dev), "int-level",
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¶m, sizeof(param)) > 0) {
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sc->sc_interrupt_cfg |= SOTG_INTERRUPT_CFG_INTLVL;
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}
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/* initialise some bus fields */
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sc->sc_bus.parent = dev;
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sc->sc_bus.devices = sc->sc_devices;
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@ -168,7 +180,7 @@ saf1761_otg_fdt_attach(device_t dev)
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}
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rid = 0;
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sc->sc_io_res =
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bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
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bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (!sc->sc_io_res) {
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goto error;
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@ -243,7 +255,7 @@ saf1761_otg_fdt_detach(device_t dev)
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sc->sc_irq_res = NULL;
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}
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if (sc->sc_io_res) {
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bus_release_resource(dev, SYS_RES_IOPORT, 0,
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bus_release_resource(dev, SYS_RES_MEMORY, 0,
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sc->sc_io_res);
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sc->sc_io_res = NULL;
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}
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