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Fix L2 cache write-back invalidate for Sheeva core.

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Submitted by:	Michal Dubiel
Obtained from:	Netasq, Semihalf
This commit is contained in:
Grzegorz Bernacki 2013-05-16 09:43:04 +00:00
parent a385d0b340
commit 0a98e01821
1 changed files with 8 additions and 0 deletions
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8
sys/arm/arm/cpufunc_asm_sheeva.S
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@ -377,9 +377,17 @@ ENTRY(sheeva_l2cache_wb_range)
END(sheeva_l2cache_wb_range)
ENTRY(sheeva_l2cache_wbinv_all)
/* Disable irqs */
mrs r1, cpsr
orr r2, r1, #I32_bit | F32_bit
msr cpsr_c, r2
mov r0, #0
mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */
mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */
msr cpsr_c, r1 /* Reenable irqs */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(sheeva_l2cache_wbinv_all)