Add support for the Microchip/Micrel KSZ9031 Gigabit Ethernet PHY.
Tested on uBMC and uFW. Sponsored by: Rubicon Communications (Netgate)
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@ -67,6 +67,14 @@ __FBSDID("$FreeBSD$");
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#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
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#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
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#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
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/* KSZ9031 */
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#define MII_KSZ9031_MMD_ACCESS_CTRL 0x0d
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#define MII_KSZ9031_MMD_ACCESS_DATA 0x0e
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#define MII_KSZ9031_MMD_DATA_NOINC (1 << 14)
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#define MII_KSZ9031_CONTROL_PAD_SKEW 0x4
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#define MII_KSZ9031_RX_DATA_PAD_SKEW 0x5
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#define MII_KSZ9031_TX_DATA_PAD_SKEW 0x6
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#define MII_KSZ9031_CLOCK_PAD_SKEW 0x8
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#define PS_TO_REG(p) ((p) / 200)
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@ -95,6 +103,7 @@ DRIVER_MODULE(micphy, miibus, micphy_driver, micphy_devclass, 0, 0);
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static const struct mii_phydesc micphys[] = {
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MII_PHY_DESC(MICREL, KSZ9021),
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MII_PHY_DESC(MICREL, KSZ9031),
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MII_PHY_END
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};
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@ -104,48 +113,128 @@ static const struct mii_phy_funcs micphy_funcs = {
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mii_phy_reset
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};
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static uint32_t
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ksz9031_read(struct mii_softc *sc, uint32_t devaddr, uint32_t reg)
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{
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/* Set up device address and register. */
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL, devaddr);
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, reg);
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/* Select register data for MMD and read the value. */
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL,
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MII_KSZ9031_MMD_DATA_NOINC | devaddr);
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return (PHY_READ(sc, MII_KSZ9031_MMD_ACCESS_DATA));
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}
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static void
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micphy_write(struct mii_softc *sc, uint32_t reg, uint32_t val)
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ksz9031_write(struct mii_softc *sc, uint32_t devaddr, uint32_t reg,
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uint32_t val)
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{
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/* Set up device address and register. */
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL, devaddr);
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, reg);
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/* Select register data for MMD and write the value. */
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL,
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MII_KSZ9031_MMD_DATA_NOINC | devaddr);
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PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, val);
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}
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static uint32_t
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ksz9021_read(struct mii_softc *sc, uint32_t reg)
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{
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PHY_WRITE(sc, MII_KSZPHY_EXTREG, reg);
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return (PHY_READ(sc, MII_KSZPHY_EXTREG_READ));
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}
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static void
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ksz9021_write(struct mii_softc *sc, uint32_t reg, uint32_t val)
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{
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PHY_WRITE(sc, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | reg);
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PHY_WRITE(sc, MII_KSZPHY_EXTREG_WRITE, val);
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}
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static int
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ksz9021_load_values(struct mii_softc *sc, phandle_t node, uint32_t reg,
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char *field1, char *field2,
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char *field3, char *field4)
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static void
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ksz90x1_load_values(struct mii_softc *sc, phandle_t node,
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uint32_t dev, uint32_t reg, char *field1, uint32_t f1mask, int f1off,
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char *field2, uint32_t f2mask, int f2off, char *field3, uint32_t f3mask,
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int f3off, char *field4, uint32_t f4mask, int f4off)
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{
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pcell_t dts_value[1];
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int len;
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int val;
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val = 0;
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if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031)
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val = ksz9031_read(sc, dev, reg);
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else
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val = ksz9021_read(sc, reg);
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if ((len = OF_getproplen(node, field1)) > 0) {
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OF_getencprop(node, field1, dts_value, len);
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val = PS_TO_REG(dts_value[0]);
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val &= ~(f1mask << f1off);
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val |= (PS_TO_REG(dts_value[0]) & f1mask) << f1off;
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}
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if ((len = OF_getproplen(node, field2)) > 0) {
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if (field2 != NULL && (len = OF_getproplen(node, field2)) > 0) {
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OF_getencprop(node, field2, dts_value, len);
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val |= PS_TO_REG(dts_value[0]) << 4;
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val &= ~(f2mask << f2off);
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val |= (PS_TO_REG(dts_value[0]) & f2mask) << f2off;
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}
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if ((len = OF_getproplen(node, field3)) > 0) {
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if (field3 != NULL && (len = OF_getproplen(node, field3)) > 0) {
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OF_getencprop(node, field3, dts_value, len);
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val |= PS_TO_REG(dts_value[0]) << 8;
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val &= ~(f3mask << f3off);
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val |= (PS_TO_REG(dts_value[0]) & f3mask) << f3off;
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}
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if ((len = OF_getproplen(node, field4)) > 0) {
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if (field4 != NULL && (len = OF_getproplen(node, field4)) > 0) {
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OF_getencprop(node, field4, dts_value, len);
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val |= PS_TO_REG(dts_value[0]) << 12;
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val &= ~(f4mask << f4off);
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val |= (PS_TO_REG(dts_value[0]) & f4mask) << f4off;
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}
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micphy_write(sc, reg, val);
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if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031)
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ksz9031_write(sc, dev, reg, val);
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else
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ksz9021_write(sc, reg, val);
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}
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return (0);
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static void
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ksz9031_load_values(struct mii_softc *sc, phandle_t node)
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{
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ksz90x1_load_values(sc, node, 2, MII_KSZ9031_CONTROL_PAD_SKEW,
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"txen-skew-ps", 0xf, 0, "rxdv-skew-ps", 0xf, 4,
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NULL, 0, 0, NULL, 0, 0);
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ksz90x1_load_values(sc, node, 2, MII_KSZ9031_RX_DATA_PAD_SKEW,
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"rxd0-skew-ps", 0xf, 0, "rxd1-skew-ps", 0xf, 4,
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"rxd2-skew-ps", 0xf, 8, "rxd3-skew-ps", 0xf, 12);
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ksz90x1_load_values(sc, node, 2, MII_KSZ9031_TX_DATA_PAD_SKEW,
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"txd0-skew-ps", 0xf, 0, "txd1-skew-ps", 0xf, 4,
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"txd2-skew-ps", 0xf, 8, "txd3-skew-ps", 0xf, 12);
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ksz90x1_load_values(sc, node, 2, MII_KSZ9031_CLOCK_PAD_SKEW,
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"rxc-skew-ps", 0x1f, 0, "txc-skew-ps", 0x1f, 5,
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NULL, 0, 0, NULL, 0, 0);
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}
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static void
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ksz9021_load_values(struct mii_softc *sc, phandle_t node)
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{
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ksz90x1_load_values(sc, node, 0, MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
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"txen-skew-ps", 0xf, 0, "txc-skew-ps", 0xf, 4,
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"rxdv-skew-ps", 0xf, 8, "rxc-skew-ps", 0xf, 12);
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ksz90x1_load_values(sc, node, 0, MII_KSZPHY_RX_DATA_PAD_SKEW,
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"rxd0-skew-ps", 0xf, 0, "rxd1-skew-ps", 0xf, 4,
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"rxd2-skew-ps", 0xf, 8, "rxd3-skew-ps", 0xf, 12);
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ksz90x1_load_values(sc, node, 0, MII_KSZPHY_TX_DATA_PAD_SKEW,
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"txd0-skew-ps", 0xf, 0, "txd1-skew-ps", 0xf, 4,
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"txd2-skew-ps", 0xf, 8, "txd3-skew-ps", 0xf, 12);
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}
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static int
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@ -174,17 +263,10 @@ micphy_attach(device_t dev)
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if ((node = ofw_bus_get_node(parent)) == -1)
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return (ENXIO);
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ksz9021_load_values(sc, node, MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
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"txen-skew-ps", "txc-skew-ps",
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"rxdv-skew-ps", "rxc-skew-ps");
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ksz9021_load_values(sc, node, MII_KSZPHY_RX_DATA_PAD_SKEW,
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"rxd0-skew-ps", "rxd1-skew-ps",
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"rxd2-skew-ps", "rxd3-skew-ps");
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ksz9021_load_values(sc, node, MII_KSZPHY_TX_DATA_PAD_SKEW,
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"txd0-skew-ps", "txd1-skew-ps",
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"txd2-skew-ps", "txd3-skew-ps");
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if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031)
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ksz9031_load_values(sc, node);
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else
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ksz9021_load_values(sc, node);
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return (0);
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}
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@ -283,6 +283,7 @@ model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY
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/* Micrel PHYs */
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model MICREL KSZ9021 0x0021 Micrel KSZ9021 10/100/1000 PHY
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model MICREL KSZ9031 0x0022 Micrel KSZ9031 10/100/1000 PHY
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/* Myson Technology PHYs */
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model xxMYSON MTD972 0x0000 MTD972 10/100 media interface
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