From 0c2d317cd24e9813f104572a86e7c9cebd1fd70e Mon Sep 17 00:00:00 2001 From: br Date: Sat, 19 Nov 2016 18:03:46 +0000 Subject: [PATCH] Enable SMP on Ingenic JZ4780. It is required to proceed full cache flush before we can use wait instruction on multicore, so use nop instead for now. Submitted by: kan Sponsored by: DARPA, AFRL --- sys/mips/conf/JZ4780 | 2 +- sys/mips/mips/exception.S | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/sys/mips/conf/JZ4780 b/sys/mips/conf/JZ4780 index 3df33a1cdb2e..2b7335af2269 100644 --- a/sys/mips/conf/JZ4780 +++ b/sys/mips/conf/JZ4780 @@ -53,7 +53,7 @@ options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required #options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed # Make an SMP-capable kernel by default -# options SMP # Symmetric MultiProcessor Kernel +options SMP # Symmetric MultiProcessor Kernel device loop device ether diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S index 04614737ab99..7262a3665f65 100644 --- a/sys/mips/mips/exception.S +++ b/sys/mips/mips/exception.S @@ -590,7 +590,11 @@ GLOBAL(MipsWaitStart) # this is 16 byte aligned mtc0 t1, MIPS_COP_0_STATUS bnez v0, MipsWaitEnd nop +#if defined(CPU_XBURST) && defined(SMP) + nop +#else wait +#endif GLOBAL(MipsWaitEnd) # MipsWaitStart + 16 jr ra PTR_ADDU sp, sp, CALLFRAME_SIZ