Add driver for Synchronous Audio Interface (SAI).
SAI supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, TDM, and codec/DSP interfaces.
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@ -29,4 +29,5 @@ arm/freescale/vybrid/vf_nfc.c optional nand
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arm/freescale/vybrid/vf_ehci.c optional ehci
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arm/freescale/vybrid/vf_gpio.c optional gpio
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arm/freescale/vybrid/vf_uart.c optional uart
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arm/freescale/vybrid/vf_sai.c optional sound
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dev/ffec/if_ffec.c optional ffec
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802
sys/arm/freescale/vybrid/vf_sai.c
Normal file
802
sys/arm/freescale/vybrid/vf_sai.c
Normal file
@ -0,0 +1,802 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vybrid Family Synchronous Audio Interface (SAI)
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* Chapter 51, Vybrid Reference Manual, Rev. 5, 07/2013
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/chip.h>
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#include <mixer_if.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/freescale/vybrid/vf_common.h>
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#include <arm/freescale/vybrid/vf_dmamux.h>
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#include <arm/freescale/vybrid/vf_edma.h>
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#define I2S_TCSR 0x00 /* SAI Transmit Control */
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#define I2S_TCR1 0x04 /* SAI Transmit Configuration 1 */
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#define I2S_TCR2 0x08 /* SAI Transmit Configuration 2 */
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#define I2S_TCR3 0x0C /* SAI Transmit Configuration 3 */
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#define I2S_TCR4 0x10 /* SAI Transmit Configuration 4 */
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#define I2S_TCR5 0x14 /* SAI Transmit Configuration 5 */
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#define I2S_TDR0 0x20 /* SAI Transmit Data */
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#define I2S_TFR0 0x40 /* SAI Transmit FIFO */
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#define I2S_TMR 0x60 /* SAI Transmit Mask */
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#define I2S_RCSR 0x80 /* SAI Receive Control */
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#define I2S_RCR1 0x84 /* SAI Receive Configuration 1 */
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#define I2S_RCR2 0x88 /* SAI Receive Configuration 2 */
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#define I2S_RCR3 0x8C /* SAI Receive Configuration 3 */
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#define I2S_RCR4 0x90 /* SAI Receive Configuration 4 */
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#define I2S_RCR5 0x94 /* SAI Receive Configuration 5 */
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#define I2S_RDR0 0xA0 /* SAI Receive Data */
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#define I2S_RFR0 0xC0 /* SAI Receive FIFO */
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#define I2S_RMR 0xE0 /* SAI Receive Mask */
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#define TCR1_TFW_M 0x1f /* Transmit FIFO Watermark Mask */
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#define TCR1_TFW_S 0 /* Transmit FIFO Watermark Shift */
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#define TCR2_MSEL_M 0x3 /* MCLK Select Mask*/
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#define TCR2_MSEL_S 26 /* MCLK Select Shift*/
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#define TCR2_BCP (1 << 25) /* Bit Clock Polarity */
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#define TCR2_BCD (1 << 24) /* Bit Clock Direction */
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#define TCR3_TCE (1 << 16) /* Transmit Channel Enable */
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#define TCR4_FRSZ_M 0x1f /* Frame size Mask */
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#define TCR4_FRSZ_S 16 /* Frame size Shift */
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#define TCR4_SYWD_M 0x1f /* Sync Width Mask */
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#define TCR4_SYWD_S 8 /* Sync Width Shift */
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#define TCR4_MF (1 << 4) /* MSB First */
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#define TCR4_FSE (1 << 3) /* Frame Sync Early */
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#define TCR4_FSP (1 << 1) /* Frame Sync Polarity Low */
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#define TCR4_FSD (1 << 0) /* Frame Sync Direction Master */
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#define TCR5_FBT_M 0x1f /* First Bit Shifted */
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#define TCR5_FBT_S 8 /* First Bit Shifted */
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#define TCR5_W0W_M 0x1f /* Word 0 Width */
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#define TCR5_W0W_S 16 /* Word 0 Width */
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#define TCR5_WNW_M 0x1f /* Word N Width */
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#define TCR5_WNW_S 24 /* Word N Width */
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#define TCSR_TE (1 << 31) /* Transmitter Enable */
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#define TCSR_BCE (1 << 28) /* Bit Clock Enable */
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#define TCSR_FRDE (1 << 0) /* FIFO Request DMA Enable */
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#define SAI_NCHANNELS 1
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static MALLOC_DEFINE(M_SAI, "sai", "sai audio");
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struct sai_rate {
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uint32_t speed;
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uint32_t div; /* Bit Clock Divide. Division value is (div + 1) * 2. */
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uint32_t mfi; /* PLL4 Multiplication Factor Integer */
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uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
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uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
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};
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/*
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* Bit clock divider formula
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* (div + 1) * 2 = MCLK/(nch * LRCLK * bits/1000000),
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* where:
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* MCLK - master clock
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* nch - number of channels
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* LRCLK - left right clock
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* e.g. (div + 1) * 2 = 16.9344/(2 * 44100 * 24/1000000)
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*
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* Example for 96khz, 24bit, 18.432 Mhz mclk (192fs)
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* { 96000, 1, 18, 40176000, 93000000 },
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*/
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static struct sai_rate rate_map[] = {
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{ 44100, 7, 33, 80798400, 93000000 }, /* 33.8688 Mhz */
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{ 96000, 3, 36, 80352000, 93000000 }, /* 36.864 Mhz */
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{ 192000, 1, 36, 80352000, 93000000 }, /* 36.864 Mhz */
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{ 0, 0 },
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};
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struct sc_info {
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struct resource *res[2];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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struct mtx *lock;
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uint32_t speed;
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uint32_t period;
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void *ih;
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int pos;
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int dma_size;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_addr_t buf_base_phys;
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uint32_t *buf_base;
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struct tcd_conf *tcd;
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struct sai_rate *sr;
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struct edma_softc *edma_sc;
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int edma_chnum;
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};
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/* Channel registers */
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struct sc_chinfo {
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct sc_pcminfo *parent;
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/* Channel information */
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uint32_t dir;
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uint32_t format;
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/* Flags */
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uint32_t run;
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};
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/* PCM device private data */
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struct sc_pcminfo {
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device_t dev;
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uint32_t (*ih) (struct sc_pcminfo *scp);
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uint32_t chnum;
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struct sc_chinfo chan[SAI_NCHANNELS];
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struct sc_info *sc;
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};
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static struct resource_spec sai_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int setup_dma(struct sc_pcminfo *scp);
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static void setup_sai(struct sc_info *);
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static void sai_configure_clock(struct sc_info *);
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/*
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* Mixer interface.
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*/
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static int
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saimixer_init(struct snd_mixer *m)
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{
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struct sc_pcminfo *scp;
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struct sc_info *sc;
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int mask;
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scp = mix_getdevinfo(m);
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sc = scp->sc;
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if (sc == NULL)
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return -1;
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mask = SOUND_MASK_PCM;
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snd_mtxlock(sc->lock);
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pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
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mix_setdevs(m, mask);
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snd_mtxunlock(sc->lock);
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return (0);
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}
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static int
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saimixer_set(struct snd_mixer *m, unsigned dev,
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unsigned left, unsigned right)
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{
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struct sc_pcminfo *scp;
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scp = mix_getdevinfo(m);
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#if 0
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device_printf(scp->dev, "saimixer_set() %d %d\n",
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left, right);
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#endif
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return (0);
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}
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static kobj_method_t saimixer_methods[] = {
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KOBJMETHOD(mixer_init, saimixer_init),
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KOBJMETHOD(mixer_set, saimixer_set),
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KOBJMETHOD_END
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};
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MIXER_DECLARE(saimixer);
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/*
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* Channel interface.
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*/
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static void *
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saichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
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struct pcm_channel *c, int dir)
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{
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struct sc_pcminfo *scp;
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struct sc_chinfo *ch;
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struct sc_info *sc;
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scp = (struct sc_pcminfo *)devinfo;
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sc = scp->sc;
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snd_mtxlock(sc->lock);
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ch = &scp->chan[0];
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ch->dir = dir;
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ch->run = 0;
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ch->buffer = b;
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ch->channel = c;
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ch->parent = scp;
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snd_mtxunlock(sc->lock);
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if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
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device_printf(scp->dev, "Can't setup sndbuf.\n");
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return NULL;
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}
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return ch;
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}
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static int
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saichan_free(kobj_t obj, void *data)
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{
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struct sc_chinfo *ch = data;
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struct sc_pcminfo *scp = ch->parent;
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struct sc_info *sc = scp->sc;
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#if 0
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device_printf(scp->dev, "saichan_free()\n");
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#endif
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snd_mtxlock(sc->lock);
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/* TODO: free channel buffer */
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snd_mtxunlock(sc->lock);
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return (0);
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}
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static int
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saichan_setformat(kobj_t obj, void *data, uint32_t format)
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{
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struct sc_chinfo *ch = data;
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ch->format = format;
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return (0);
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}
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static uint32_t
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saichan_setspeed(kobj_t obj, void *data, uint32_t speed)
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{
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struct sc_pcminfo *scp;
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struct sc_chinfo *ch;
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struct sai_rate *sr;
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struct sc_info *sc;
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int threshold;
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int i;
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ch = data;
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scp = ch->parent;
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sc = scp->sc;
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sr = NULL;
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/* First look for equal frequency. */
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for (i = 0; rate_map[i].speed != 0; i++) {
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if (rate_map[i].speed == speed)
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sr = &rate_map[i];
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}
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/* If no match, just find nearest. */
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if (sr == NULL) {
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for (i = 0; rate_map[i].speed != 0; i++) {
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sr = &rate_map[i];
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threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
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((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
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if (speed < threshold)
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break;
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}
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}
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sc->sr = sr;
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sai_configure_clock(sc);
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return (sr->speed);
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}
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static void
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sai_configure_clock(struct sc_info *sc)
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{
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struct sai_rate *sr;
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int reg;
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sr = sc->sr;
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/*
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* Manual says that TCR/RCR registers must not be
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* altered when TCSR[TE] is set.
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* We ignore it since we have problem sometimes
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* after re-enabling transmitter (DMA goes stall).
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*/
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reg = READ4(sc, I2S_TCR2);
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reg &= ~(0xff << 0);
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reg |= (sr->div << 0);
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WRITE4(sc, I2S_TCR2, reg);
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pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
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}
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static uint32_t
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saichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
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{
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struct sc_chinfo *ch = data;
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struct sc_pcminfo *scp = ch->parent;
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struct sc_info *sc = scp->sc;
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sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
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sc->period = sndbuf_getblksz(ch->buffer);
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return (sc->period);
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}
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uint32_t sai_dma_intr(void *arg, int chn);
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uint32_t
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sai_dma_intr(void *arg, int chn)
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{
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struct sc_pcminfo *scp;
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struct sc_chinfo *ch;
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struct sc_info *sc;
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struct tcd_conf *tcd;
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scp = arg;
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ch = &scp->chan[0];
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sc = scp->sc;
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tcd = sc->tcd;
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sc->pos += (tcd->nbytes * tcd->nmajor);
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if (sc->pos >= sc->dma_size)
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sc->pos -= sc->dma_size;
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chn_intr(ch->channel);
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return (0);
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}
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static int
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find_edma_controller(struct sc_info *sc)
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{
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struct edma_softc *edma_sc;
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phandle_t node, edma_node;
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int edma_src_transmit;
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int edma_mux_group;
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int edma_device_id;
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device_t edma_dev;
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int dts_value;
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int len;
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int i;
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if ((node = ofw_bus_get_node(sc->dev)) == -1)
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return (ENXIO);
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if ((len = OF_getproplen(node, "edma-controller")) <= 0)
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return (ENXIO);
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if ((len = OF_getproplen(node, "edma-src-transmit")) <= 0)
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return (ENXIO);
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if ((len = OF_getproplen(node, "edma-mux-group")) <= 0)
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return (ENXIO);
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OF_getprop(node, "edma-src-transmit", &dts_value, len);
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edma_src_transmit = fdt32_to_cpu(dts_value);
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OF_getprop(node, "edma-mux-group", &dts_value, len);
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edma_mux_group = fdt32_to_cpu(dts_value);
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OF_getprop(node, "edma-controller", &dts_value, len);
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edma_node = OF_xref_phandle(fdt32_to_cpu(dts_value));
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if ((len = OF_getproplen(edma_node, "device-id")) <= 0) {
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return (ENXIO);
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};
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OF_getprop(edma_node, "device-id", &dts_value, len);
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edma_device_id = fdt32_to_cpu(dts_value);
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edma_sc = NULL;
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for (i = 0; i < EDMA_NUM_DEVICES; i++) {
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edma_dev = devclass_get_device(devclass_find("edma"), i);
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if (edma_dev) {
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edma_sc = device_get_softc(edma_dev);
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if (edma_sc->device_id == edma_device_id) {
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/* found */
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break;
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};
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||||
edma_sc = NULL;
|
||||
};
|
||||
};
|
||||
|
||||
if (edma_sc == NULL) {
|
||||
device_printf(sc->dev, "no eDMA. can't operate\n");
|
||||
return (ENXIO);
|
||||
};
|
||||
|
||||
sc->edma_sc = edma_sc;
|
||||
|
||||
sc->edma_chnum = edma_sc->channel_configure(edma_sc, edma_mux_group,
|
||||
edma_src_transmit);
|
||||
if (sc->edma_chnum < 0) {
|
||||
/* cant setup eDMA */
|
||||
return (ENXIO);
|
||||
};
|
||||
|
||||
return (0);
|
||||
};
|
||||
|
||||
static int
|
||||
setup_dma(struct sc_pcminfo *scp)
|
||||
{
|
||||
struct tcd_conf *tcd;
|
||||
struct sc_info *sc;
|
||||
|
||||
sc = scp->sc;
|
||||
|
||||
tcd = malloc(sizeof(struct tcd_conf), M_DEVBUF, M_WAITOK | M_ZERO);
|
||||
tcd->channel = sc->edma_chnum;
|
||||
tcd->ih = sai_dma_intr;
|
||||
tcd->ih_user = scp;
|
||||
tcd->saddr = sc->buf_base_phys;
|
||||
tcd->daddr = rman_get_start(sc->res[0]) + I2S_TDR0;
|
||||
|
||||
/*
|
||||
* Bytes to transfer per each minor loop.
|
||||
* Hardware FIFO buffer size is 32x32bits.
|
||||
*/
|
||||
tcd->nbytes = 64;
|
||||
|
||||
tcd->nmajor = 512;
|
||||
tcd->smod = 18; /* dma_size range */
|
||||
tcd->dmod = 0;
|
||||
tcd->esg = 0;
|
||||
tcd->soff = 0x4;
|
||||
tcd->doff = 0;
|
||||
tcd->ssize = 0x2;
|
||||
tcd->dsize = 0x2;
|
||||
tcd->slast = 0;
|
||||
tcd->dlast_sga = 0;
|
||||
|
||||
sc->tcd = tcd;
|
||||
|
||||
sc->edma_sc->dma_setup(sc->edma_sc, sc->tcd);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
saichan_trigger(kobj_t obj, void *data, int go)
|
||||
{
|
||||
struct sc_chinfo *ch = data;
|
||||
struct sc_pcminfo *scp = ch->parent;
|
||||
struct sc_info *sc = scp->sc;
|
||||
|
||||
snd_mtxlock(sc->lock);
|
||||
|
||||
switch (go) {
|
||||
case PCMTRIG_START:
|
||||
#if 0
|
||||
device_printf(scp->dev, "trigger start\n");
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PCMTRIG_STOP:
|
||||
case PCMTRIG_ABORT:
|
||||
#if 0
|
||||
device_printf(scp->dev, "trigger stop or abort\n");
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
snd_mtxunlock(sc->lock);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
saichan_getptr(kobj_t obj, void *data)
|
||||
{
|
||||
struct sc_pcminfo *scp;
|
||||
struct sc_chinfo *ch;
|
||||
struct sc_info *sc;
|
||||
|
||||
ch = data;
|
||||
scp = ch->parent;
|
||||
sc = scp->sc;
|
||||
|
||||
return (sc->pos);
|
||||
}
|
||||
|
||||
static uint32_t sai_pfmt[] = {
|
||||
/*
|
||||
* eDMA doesn't allow 24-bit coping,
|
||||
* so we use 32.
|
||||
*/
|
||||
SND_FORMAT(AFMT_S32_LE, 2, 0),
|
||||
0
|
||||
};
|
||||
|
||||
static struct pcmchan_caps sai_pcaps = {44100, 192000, sai_pfmt, 0};
|
||||
|
||||
static struct pcmchan_caps *
|
||||
saichan_getcaps(kobj_t obj, void *data)
|
||||
{
|
||||
|
||||
return (&sai_pcaps);
|
||||
}
|
||||
|
||||
static kobj_method_t saichan_methods[] = {
|
||||
KOBJMETHOD(channel_init, saichan_init),
|
||||
KOBJMETHOD(channel_free, saichan_free),
|
||||
KOBJMETHOD(channel_setformat, saichan_setformat),
|
||||
KOBJMETHOD(channel_setspeed, saichan_setspeed),
|
||||
KOBJMETHOD(channel_setblocksize, saichan_setblocksize),
|
||||
KOBJMETHOD(channel_trigger, saichan_trigger),
|
||||
KOBJMETHOD(channel_getptr, saichan_getptr),
|
||||
KOBJMETHOD(channel_getcaps, saichan_getcaps),
|
||||
KOBJMETHOD_END
|
||||
};
|
||||
CHANNEL_DECLARE(saichan);
|
||||
|
||||
static int
|
||||
sai_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (!ofw_bus_is_compatible(dev, "fsl,mvf600-sai"))
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "Vybrid Family Synchronous Audio Interface");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static void
|
||||
sai_intr(void *arg)
|
||||
{
|
||||
struct sc_pcminfo *scp;
|
||||
struct sc_info *sc;
|
||||
|
||||
scp = arg;
|
||||
sc = scp->sc;
|
||||
|
||||
device_printf(sc->dev, "Error I2S_TCSR == 0x%08x\n",
|
||||
READ4(sc, I2S_TCSR));
|
||||
}
|
||||
|
||||
static void
|
||||
setup_sai(struct sc_info *sc)
|
||||
{
|
||||
int reg;
|
||||
|
||||
/*
|
||||
* TCR/RCR registers must not be altered when TCSR[TE] is set.
|
||||
*/
|
||||
|
||||
reg = READ4(sc, I2S_TCSR);
|
||||
reg &= ~(TCSR_BCE | TCSR_TE | TCSR_FRDE);
|
||||
WRITE4(sc, I2S_TCSR, reg);
|
||||
|
||||
reg = READ4(sc, I2S_TCR3);
|
||||
reg &= ~(TCR3_TCE);
|
||||
WRITE4(sc, I2S_TCR3, reg);
|
||||
|
||||
reg = (64 << TCR1_TFW_S);
|
||||
WRITE4(sc, I2S_TCR1, reg);
|
||||
|
||||
reg = READ4(sc, I2S_TCR2);
|
||||
reg &= ~(TCR2_MSEL_M << TCR2_MSEL_S);
|
||||
reg |= (1 << TCR2_MSEL_S);
|
||||
reg |= (TCR2_BCP | TCR2_BCD);
|
||||
WRITE4(sc, I2S_TCR2, reg);
|
||||
|
||||
sai_configure_clock(sc);
|
||||
|
||||
reg = READ4(sc, I2S_TCR3);
|
||||
reg |= (TCR3_TCE);
|
||||
WRITE4(sc, I2S_TCR3, reg);
|
||||
|
||||
/* Configure to 32-bit I2S mode */
|
||||
reg = READ4(sc, I2S_TCR4);
|
||||
reg &= ~(TCR4_FRSZ_M << TCR4_FRSZ_S);
|
||||
reg |= (1 << TCR4_FRSZ_S); /* 2 words per frame */
|
||||
reg &= ~(TCR4_SYWD_M << TCR4_SYWD_S);
|
||||
reg |= (23 << TCR4_SYWD_S);
|
||||
reg |= (TCR4_MF | TCR4_FSE | TCR4_FSP | TCR4_FSD);
|
||||
WRITE4(sc, I2S_TCR4, reg);
|
||||
|
||||
reg = READ4(sc, I2S_TCR5);
|
||||
reg &= ~(TCR5_W0W_M << TCR5_W0W_S);
|
||||
reg |= (23 << TCR5_W0W_S);
|
||||
reg &= ~(TCR5_WNW_M << TCR5_WNW_S);
|
||||
reg |= (23 << TCR5_WNW_S);
|
||||
reg &= ~(TCR5_FBT_M << TCR5_FBT_S);
|
||||
reg |= (31 << TCR5_FBT_S);
|
||||
WRITE4(sc, I2S_TCR5, reg);
|
||||
|
||||
/* Enable transmitter */
|
||||
reg = READ4(sc, I2S_TCSR);
|
||||
reg |= (TCSR_BCE | TCSR_TE | TCSR_FRDE);
|
||||
reg |= (1 << 10); /* FEIE */
|
||||
WRITE4(sc, I2S_TCSR, reg);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
sai_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
|
||||
{
|
||||
bus_addr_t *addr;
|
||||
|
||||
if (err)
|
||||
return;
|
||||
|
||||
addr = (bus_addr_t*)arg;
|
||||
*addr = segs[0].ds_addr;
|
||||
}
|
||||
|
||||
static int
|
||||
sai_attach(device_t dev)
|
||||
{
|
||||
char status[SND_STATUSLEN];
|
||||
struct sc_pcminfo *scp;
|
||||
struct sc_info *sc;
|
||||
int err;
|
||||
|
||||
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
|
||||
sc->dev = dev;
|
||||
sc->sr = &rate_map[0];
|
||||
sc->pos = 0;
|
||||
|
||||
sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sai softc");
|
||||
if (sc->lock == NULL) {
|
||||
device_printf(dev, "Cant create mtx\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
if (bus_alloc_resources(dev, sai_spec, sc->res)) {
|
||||
device_printf(dev, "could not allocate resources\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/* Memory interface */
|
||||
sc->bst = rman_get_bustag(sc->res[0]);
|
||||
sc->bsh = rman_get_bushandle(sc->res[0]);
|
||||
|
||||
/* eDMA */
|
||||
if (find_edma_controller(sc)) {
|
||||
device_printf(dev, "could not find active eDMA\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/* Setup PCM */
|
||||
scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
scp->sc = sc;
|
||||
scp->dev = dev;
|
||||
|
||||
/* DMA */
|
||||
sc->dma_size = 262144;
|
||||
|
||||
/*
|
||||
* Must use dma_size boundary as modulo feature required.
|
||||
* Modulo feature allows setup circular buffer.
|
||||
*/
|
||||
|
||||
err = bus_dma_tag_create(
|
||||
bus_get_dma_tag(sc->dev),
|
||||
4, sc->dma_size, /* alignment, boundary */
|
||||
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
||||
BUS_SPACE_MAXADDR, /* highaddr */
|
||||
NULL, NULL, /* filter, filterarg */
|
||||
sc->dma_size, 1, /* maxsize, nsegments */
|
||||
sc->dma_size, 0, /* maxsegsize, flags */
|
||||
NULL, NULL, /* lockfunc, lockarg */
|
||||
&sc->dma_tag);
|
||||
|
||||
err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
|
||||
BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
|
||||
if (err) {
|
||||
device_printf(dev, "cannot allocate framebuffer\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
|
||||
sc->dma_size, sai_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
|
||||
if (err) {
|
||||
device_printf(dev, "cannot load DMA map\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
bzero(sc->buf_base, sc->dma_size);
|
||||
|
||||
/* Setup interrupt handler */
|
||||
err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
|
||||
NULL, sai_intr, scp, &sc->ih);
|
||||
if (err) {
|
||||
device_printf(dev, "Unable to alloc interrupt resource.\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
|
||||
|
||||
err = pcm_register(dev, scp, 1, 0);
|
||||
if (err) {
|
||||
device_printf(dev, "Can't register pcm.\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
scp->chnum = 0;
|
||||
pcm_addchan(dev, PCMDIR_PLAY, &saichan_class, scp);
|
||||
scp->chnum++;
|
||||
|
||||
snprintf(status, SND_STATUSLEN, "at simplebus");
|
||||
pcm_setstatus(dev, status);
|
||||
|
||||
mixer_init(dev, &saimixer_class, scp);
|
||||
|
||||
setup_dma(scp);
|
||||
setup_sai(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t sai_pcm_methods[] = {
|
||||
DEVMETHOD(device_probe, sai_probe),
|
||||
DEVMETHOD(device_attach, sai_attach),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t sai_pcm_driver = {
|
||||
"pcm",
|
||||
sai_pcm_methods,
|
||||
PCM_SOFTC_SIZE,
|
||||
};
|
||||
|
||||
DRIVER_MODULE(sai, simplebus, sai_pcm_driver, pcm_devclass, 0, 0);
|
||||
MODULE_DEPEND(sai, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
||||
MODULE_VERSION(sai, 1);
|
||||
@ -311,6 +311,9 @@
|
||||
interrupt-parent = <&GIC>;
|
||||
status = "disabled";
|
||||
edma-controller = <&edma1>;
|
||||
edma-src-receive = < 8 >;
|
||||
edma-src-transmit = < 9 >;
|
||||
edma-mux-group = < 1 >;
|
||||
clock_names = "sai3", "cko1";
|
||||
iomux_config = < 16 0x2
|
||||
19 0x2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user