Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.
This makes elf_aux_info(3) useable for ARM ports. MFC after: 1 month
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@ -35,6 +35,8 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpu.h>
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#include <machine/cpuinfo.h>
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#include <machine/elf.h>
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#include <machine/md_var.h>
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#if __ARM_ARCH >= 6
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void reinit_mmu(uint32_t ttb, uint32_t aux_clr, uint32_t aux_set);
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@ -77,6 +79,9 @@ SYSCTL_INT(_hw_cpu_quirks, OID_AUTO, actlr_set,
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void
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cpuinfo_init(void)
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{
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#if __ARM_ARCH >= 6
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uint32_t tmp;
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#endif
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/*
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* Prematurely fetch CPU quirks. Standard fetch for tunable
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@ -190,6 +195,47 @@ cpuinfo_init(void)
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}
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cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
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cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
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/* Fill AT_HWCAP bits. */
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elf_hwcap |= HWCAP_HALF | HWCAP_FAST_MULT; /* Requierd for all CPUs */
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elf_hwcap |= HWCAP_TLS | HWCAP_EDSP; /* Requierd for v6+ CPUs */
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tmp = (cpuinfo.id_isar0 >> 24) & 0xF; /* Divide_instrs */
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if (tmp >= 1)
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elf_hwcap |= HWCAP_IDIVT;
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if (tmp >= 2)
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elf_hwcap |= HWCAP_IDIVA;
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tmp = (cpuinfo.id_pfr0 >> 4) & 0xF; /* State1 */
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if (tmp >= 1)
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elf_hwcap |= HWCAP_THUMB;
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tmp = (cpuinfo.id_pfr0 >> 12) & 0xF; /* State3 */
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if (tmp >= 1)
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elf_hwcap |= HWCAP_THUMBEE;
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tmp = (cpuinfo.id_mmfr0 >> 0) & 0xF; /* VMSA */
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if (tmp >= 5)
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elf_hwcap |= HWCAP_LPAE;
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/* Fill AT_HWCAP2 bits. */
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tmp = (cpuinfo.id_isar5 >> 4) & 0xF; /* AES */
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if (tmp >= 1)
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elf_hwcap2 |= HWCAP2_AES;
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if (tmp >= 2)
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elf_hwcap2 |= HWCAP2_PMULL;
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tmp = (cpuinfo.id_isar5 >> 8) & 0xF; /* SHA1 */
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if (tmp >= 1)
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elf_hwcap2 |= HWCAP2_SHA1;
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tmp = (cpuinfo.id_isar5 >> 12) & 0xF; /* SHA2 */
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if (tmp >= 1)
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elf_hwcap2 |= HWCAP2_SHA2;
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tmp = (cpuinfo.id_isar5 >> 16) & 0xF; /* CRC32 */
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if (tmp >= 1)
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elf_hwcap2 |= HWCAP2_CRC32;
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#endif
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}
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@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
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static boolean_t elf32_arm_abi_supported(struct image_params *);
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u_long elf_hwcap;
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u_long elf_hwcap2;
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struct sysentvec elf32_freebsd_sysvec = {
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.sv_size = SYS_MAXSYSCALL,
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@ -92,6 +93,7 @@ struct sysentvec elf32_freebsd_sysvec = {
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.sv_thread_detach = NULL,
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.sv_trap = NULL,
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.sv_hwcap = &elf_hwcap,
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.sv_hwcap2 = &elf_hwcap2,
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};
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INIT_SYSENTVEC(elf32_sysvec, &elf32_freebsd_sysvec);
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@ -149,6 +149,8 @@ vfp_init(void)
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(tmp & VMVFR1_I_MASK) >> VMVFR1_I_OFF == 1 &&
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(tmp & VMVFR1_SP_MASK) >> VMVFR1_SP_OFF == 1)
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elf_hwcap |= HWCAP_NEON;
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if ((tmp & VMVFR1_FMAC_MASK) >> VMVFR1_FMAC_OFF == 1)
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elf_hwcap |= HWCAP_VFPv4;
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}
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/* initialize the coprocess 10 and 11 calls
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@ -117,10 +117,36 @@ __ElfType(Auxinfo);
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#define ET_DYN_LOAD_ADDR 0x12000
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/* Flags passed in AT_HWCAP. */
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#define HWCAP_SWP 0x00000001 /* Unsupported, never set. */
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#define HWCAP_HALF 0x00000002 /* Always set. */
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#define HWCAP_THUMB 0x00000004
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#define HWCAP_26BIT 0x00000008 /* Unsupported, never set. */
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#define HWCAP_FAST_MULT 0x00000010 /* Always set. */
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#define HWCAP_FPA 0x00000020 /* Unsupported, never set. */
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#define HWCAP_VFP 0x00000040
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#define HWCAP_EDSP 0x00000080 /* Always set for ARMv6+. */
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#define HWCAP_JAVA 0x00000100 /* Unsupported, never set. */
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#define HWCAP_IWMMXT 0x00000200 /* Unsupported, never set. */
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#define HWCAP_CRUNCH 0x00000400 /* Unsupported, never set. */
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#define HWCAP_THUMBEE 0x00000800
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#define HWCAP_NEON 0x00001000
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#define HWCAP_VFPv3 0x00002000
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#define HWCAP_VFPv3D16 0x00004000
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#define HWCAP_TLS 0x00008000 /* Always set for ARMv6+. */
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#define HWCAP_VFPv4 0x00010000
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#define HWCAP_IDIVA 0x00020000
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#define HWCAP_IDIVT 0x00040000
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#define HWCAP_VFPD32 0x00080000
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#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
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#define HWCAP_LPAE 0x00100000
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#define HWCAP_EVTSTRM 0x00200000 /* Not implemented yet. */
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/* Flags passed in AT_HWCAP2. */
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#define HWCAP2_AES 0x00000001
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#define HWCAP2_PMULL 0x00000002
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#define HWCAP2_SHA1 0x00000004
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#define HWCAP2_SHA2 0x00000008
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#define HWCAP2_CRC32 0x00000010
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#endif /* !_MACHINE_ELF_H_ */
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@ -39,6 +39,7 @@ extern int szsigcode;
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extern uint32_t *vm_page_dump;
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extern int vm_page_dump_size;
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extern u_long elf_hwcap;
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extern u_long elf_hwcap2;
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extern int (*_arm_memcpy)(void *, void *, int, int);
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extern int (*_arm_bzero)(void *, int, int);
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@ -119,6 +119,12 @@
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#define VMVFR0_RB_MASK (0x0000000f) /* VFP 64 bit media support */
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/* VMVFR1 */
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#define VMVFR1_FMAC_OFF 28
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#define VMVFR1_FMAC_MASK (0xf0000000) /* Neon FMAC support */
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#define VMVFR1_VFP_HP_OFF 24
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#define VMVFR1_VFP_HP_MASK (0x0f000000) /* VFP half prec support */
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#define VMVFR1_HP_OFF 20
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#define VMVFR1_HP_MASK (0x00f00000) /* Neon half prec support */
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#define VMVFR1_SP_OFF 16
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#define VMVFR1_SP_MASK (0x000f0000) /* Neon single prec support */
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#define VMVFR1_I_OFF 12
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