MFp4: Improve asynchronous packet receive process.
- Wake up DMA engine after adding a new receive buffer. - Skip buffers which have unknown state after error. - More rigid error detection. MFC after: 1 week
This commit is contained in:
Hidetoshi Shimokawa
parent
2c70b09005
commit
0cf4488ab4
@ -2683,13 +2683,16 @@ fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt
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if ((info->flag & FWTI_BLOCK_ASY) != 0)
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r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
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if (r == sizeof(uint32_t))
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if (r == sizeof(uint32_t)) {
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/* XXX */
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device_printf(sc->fc.dev, "Unknown tcode %d\n",
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fp->mode.common.tcode);
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return (-1);
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}
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if (r > dbch->xferq.psize) {
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device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
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return (-1);
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/* panic ? */
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}
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@ -2697,7 +2700,8 @@ fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt
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}
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static void
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fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
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fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
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struct fwohcidb_tr *db_tr, uint32_t off, int wake)
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{
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struct fwohcidb *db = &db_tr->db[0];
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@ -2706,6 +2710,9 @@ fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
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FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
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fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
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dbch->bottom = db_tr;
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if (wake)
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OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
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}
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static void
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@ -2717,7 +2724,7 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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int nvec;
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struct fw_pkt *fp;
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uint8_t *ld;
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uint32_t stat, off, status;
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uint32_t stat, off, status, event;
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u_int spd;
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int len, plen, hlen, pcnt, offset;
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int s;
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@ -2740,10 +2747,13 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
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status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
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resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
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#if 0
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printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
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#endif
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while (status & OHCI_CNTL_DMA_ACTIVE) {
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#if 0
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if (off == OHCI_ARQOFF)
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printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n",
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db_tr->bus_addr, status, resCount);
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#endif
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len = dbch->xferq.psize - resCount;
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ld = (uint8_t *)db_tr->buf;
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if (dbch->pdb_tr == NULL) {
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@ -2783,8 +2793,9 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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ld += rlen;
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len -= rlen;
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hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
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if (hlen < 0) {
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printf("hlen < 0 shouldn't happen");
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if (hlen <= 0) {
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printf("hlen should be positive.");
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goto err;
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}
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offset = sizeof(pktbuf);
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vec[0].iov_base = (char *)&pktbuf;
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@ -2802,16 +2813,16 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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fp=(struct fw_pkt *)ld;
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hlen = fwohci_arcv_swap(fp, len);
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if (hlen == 0)
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/* XXX need reset */
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goto out;
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goto err;
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if (hlen < 0) {
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dbch->pdb_tr = db_tr;
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dbch->buf_offset = - dbch->buf_offset;
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/* sanity check */
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if (resCount != 0)
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printf("resCount = %d !?\n",
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resCount);
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/* XXX clear pdb_tr */
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if (resCount != 0) {
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printf("resCount=%d hlen=%d\n",
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resCount, hlen);
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goto err;
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}
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goto out;
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}
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offset = 0;
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@ -2823,8 +2834,7 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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= sizeof(fw_pkt) so this shouldn't happens */
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printf("plen(%d) is negative! offset=%d\n",
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plen, offset);
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/* XXX clear pdb_tr */
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goto out;
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goto err;
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}
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if (plen > 0) {
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len -= plen;
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@ -2833,10 +2843,12 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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if (firewire_debug)
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printf("splitted payload\n");
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/* sanity check */
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if (resCount != 0)
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printf("resCount = %d !?\n",
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resCount);
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/* XXX clear pdb_tr */
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if (resCount != 0) {
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printf("resCount=%d plen=%d"
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" len=%d\n",
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resCount, plen, len);
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goto err;
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}
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goto out;
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}
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vec[nvec].iov_base = ld;
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@ -2849,18 +2861,14 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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printf("nvec == 0\n");
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/* DMA result-code will be written at the tail of packet */
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#if BYTE_ORDER == BIG_ENDIAN
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stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
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#else
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stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
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#endif
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stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
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#if 0
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printf("plen: %d, stat %x\n",
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plen ,stat);
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#endif
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spd = (stat >> 5) & 0x3;
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stat &= 0x1f;
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switch(stat){
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spd = (stat >> 21) & 0x3;
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event = (stat >> 16) & 0x1f;
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switch (event) {
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case FWOHCIEV_ACKPEND:
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#if 0
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printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
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@ -2885,15 +2893,23 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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printf("got BUSRST packet!?\n");
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break;
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default:
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device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
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#if 0 /* XXX */
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goto out;
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device_printf(sc->fc.dev,
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"Async DMA Receive error err=%02x %s"
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" plen=%d offset=%d len=%d status=0x%08x"
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" tcode=0x%x, stat=0x%08x\n",
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event, fwohcicode[event], plen,
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dbch->buf_offset, len,
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OREAD(sc, OHCI_DMACTL(off)),
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fp->mode.common.tcode, stat);
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#if 1 /* XXX */
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goto err;
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#endif
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break;
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}
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pcnt ++;
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if (dbch->pdb_tr != NULL) {
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fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
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fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
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off, 1);
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dbch->pdb_tr = NULL;
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}
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@ -2902,7 +2918,7 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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if (resCount == 0) {
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/* done on this buffer */
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if (dbch->pdb_tr == NULL) {
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fwohci_arcv_free_buf(dbch, db_tr);
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fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
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dbch->buf_offset = 0;
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} else
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if (dbch->pdb_tr != db_tr)
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@ -2925,4 +2941,24 @@ fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
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printf("fwohci_arcv: no packets\n");
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#endif
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splx(s);
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return;
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err:
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device_printf(sc->fc.dev, "AR DMA status=%x, ",
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OREAD(sc, OHCI_DMACTL(off)));
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dbch->pdb_tr = NULL;
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/* skip until resCount != 0 */
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printf(" skip buffer");
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while (resCount == 0) {
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printf(" #");
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fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
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db_tr = STAILQ_NEXT(db_tr, link);
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resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
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& OHCI_COUNT_MASK;
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} while (resCount == 0)
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printf(" done\n");
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dbch->top = db_tr;
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dbch->buf_offset = dbch->xferq.psize - resCount;
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OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
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splx(s);
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}
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@ -396,8 +396,13 @@ struct fwohci_txpkthdr{
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}mode;
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};
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struct fwohci_trailer{
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#if BYTE_ORDER == BIG_ENDIAN
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uint32_t stat:16,
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time:16;
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#else
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uint32_t time:16,
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stat:16;
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#endif
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};
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#define OHCI_CNTL_CYCSRC (0x1 << 22)
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