Add a new trap-v6.c which has support for all armv7 exceptions. This
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
This commit is contained in:
ian
parent
927977ec7c
commit
0d41ce8792
655
sys/arm/arm/trap-v6.c
Normal file
655
sys/arm/arm/trap-v6.c
Normal file
@ -0,0 +1,655 @@
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/*-
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* Copyright 2014 Olivier Houchard <cognet@FreeBSD.org>
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* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
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* Copyright 2014 Michal Meloun <meloun@miracle.cz>
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* Copyright 2014 Andrew Turner <andrew@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_ktrace.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/signalvar.h>
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#include <sys/ktr.h>
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#ifdef KTRACE
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#include <sys/uio.h>
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#include <sys/ktrace.h>
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#endif
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_map.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_param.h>
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#include <machine/cpu.h>
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#include <machine/cpu-v6.h>
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#include <machine/frame.h>
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#include <machine/machdep.h>
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#include <machine/pcb.h>
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#include <machine/vmparam.h>
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#ifdef KDB
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#include <sys/kdb.h>
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#include <machine/db_machdep.h>
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#endif
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extern char fusubailout[];
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struct ksig {
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int sig;
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u_long code;
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vm_offset_t addr;
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};
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typedef int abort_func_t(struct trapframe *, u_int, u_int, u_int, u_int,
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struct thread *, struct ksig *);
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static abort_func_t abort_fatal;
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static abort_func_t abort_align;
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static abort_func_t abort_icache;
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struct abort {
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abort_func_t *func;
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const char *desc;
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};
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/*
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* How are the aborts handled?
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*
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* Undefined Code:
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* - Always fatal as we do not know what does it mean.
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* Imprecise External Abort:
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* - Always fatal, but can be handled somehow in the future.
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* Now, due to PCIe buggy harware, ignored.
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* Precise External Abort:
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* - Always fatal, but who knows in the future???
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* Debug Event:
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* - Special handling.
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* External Translation Abort (L1 & L2)
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* - Always fatal as something is screwed up in page tables or harware.
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* Domain Fault (L1 & L2):
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* - Always fatal as we do not play game with domains.
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* Alignment Fault:
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* - Everything should be aligned in kernel including user to kernel and
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* vice versa data copying, so we ignore pcb_onfault, and it's always fatal.
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* We generate signal in case of abort from user mode.
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* Instruction cache maintenance:
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* - According to manual, this is translation fault during cache maintenance
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* operation. So, it could be really complex in SMP case and fuzzy too
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* for cache operations working on virtual addresses. For now, we will
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* consider this abort as fatal. In fact, no cache maintenance on
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* not mapped virtual addresses should be called. As cache maintenance
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* operation (except DMB, DSB, and Flush Prefetch Buffer) are priviledged,
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* the abort is fatal for user mode as well for now. (This is good place to
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* note that cache maintenance on virtual address fill TLB.)
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* Acces Bit (L1 & L2):
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* - Fast hardware emulation for kernel and user mode.
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* Translation Fault (L1 & L2):
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* - Standard fault mechanism is held including vm_fault().
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* Permission Fault (L1 & L2):
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* - Fast harware emulation of modify bits and in other cases, standard
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* fault mechanism is held including vm_fault().
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*/
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static const struct abort aborts[] = {
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{abort_fatal, "Undefined Code (0x000)"},
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{abort_align, "Alignment Fault"},
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{abort_fatal, "Debug Event"},
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{NULL, "Access Bit (L1)"},
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{abort_icache, "Instruction cache maintenance"},
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{NULL, "Translation Fault (L1)"},
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{NULL, "Access Bit (L2)"},
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{NULL, "Translation Fault (L2)"},
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{abort_fatal, "External Abort"},
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{abort_fatal, "Domain Fault (L1)"},
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{abort_fatal, "Undefined Code (0x00A)"},
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{abort_fatal, "Domain Fault (L2)"},
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{abort_fatal, "External Translation Abort (L1)"},
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{NULL, "Permission Fault (L1)"},
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{abort_fatal, "External Translation Abort (L2)"},
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{NULL, "Permission Fault (L2)"},
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{abort_fatal, "TLB Conflict Abort"},
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{abort_fatal, "Undefined Code (0x401)"},
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{abort_fatal, "Undefined Code (0x402)"},
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{abort_fatal, "Undefined Code (0x403)"},
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{abort_fatal, "Undefined Code (0x404)"},
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{abort_fatal, "Undefined Code (0x405)"},
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{abort_fatal, "Asynchronous External Abort"},
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{abort_fatal, "Undefined Code (0x407)"},
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{abort_fatal, "Asynchronous Parity Error on Memory Access"},
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{abort_fatal, "Parity Error on Memory Access"},
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{abort_fatal, "Undefined Code (0x40A)"},
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{abort_fatal, "Undefined Code (0x40B)"},
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{abort_fatal, "Parity Error on Translation (L1)"},
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{abort_fatal, "Undefined Code (0x40D)"},
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{abort_fatal, "Parity Error on Translation (L2)"},
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{abort_fatal, "Undefined Code (0x40F)"}
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};
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static __inline void
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call_trapsignal(struct thread *td, int sig, int code, vm_offset_t addr)
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{
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ksiginfo_t ksi;
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CTR4(KTR_TRAP, "%s: addr: %#x, sig: %d, code: %d",
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__func__, addr, sig, code);
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/*
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* TODO: some info would be nice to know
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* if we are serving data or prefetch abort.
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*/
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ksiginfo_init_trap(&ksi);
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ksi.ksi_signo = sig;
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ksi.ksi_code = code;
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ksi.ksi_addr = (void *)addr;
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trapsignal(td, &ksi);
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}
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/*
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* abort_imprecise() handles the following abort:
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*
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* FAULT_EA_IMPREC - Imprecise External Abort
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*
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* The imprecise means that we don't know where the abort happened,
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* thus FAR is undefined. The abort should not never fire, but hot
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* plugging or accidental harware failure can be the cause of it.
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* If the abort happens, it can even be on different (thread) context.
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* Without any additional support, the abort is fatal, as we do not
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* know what really happened.
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*
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* QQQ: Some additional functionality, like pcb_onfault but global,
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* can be implemented. Imprecise handlers could be registered
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* which tell us if the abort is caused by something they know
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* about. They should return one of three codes like:
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* FAULT_IS_MINE,
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* FAULT_CAN_BE_MINE,
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* FAULT_IS_NOT_MINE.
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* The handlers should be called until some of them returns
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* FAULT_IS_MINE value or all was called. If all handlers return
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* FAULT_IS_NOT_MINE value, then the abort is fatal.
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*/
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static __inline void
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abort_imprecise(struct trapframe *tf, u_int fsr, u_int prefetch, u_int usermode)
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{
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/* XXXX We can got imprecise abort as result of access
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* to not-present PCI/PCIe configuration space.
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*/
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#if 0
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goto out;
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#endif
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abort_fatal(tf, FAULT_EA_IMPREC, fsr, 0, prefetch, curthread, NULL);
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/*
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* Returning from this function means that we ignore
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* the abort for good reason. Note that imprecise abort
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* could fire any time even in user mode.
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*/
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#if 0
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out:
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if (usermode)
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userret(curthread, tf);
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#endif
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}
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/*
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* abort_debug() handles the following abort:
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*
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* FAULT_DEBUG - Debug Event
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*
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*/
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static __inline void
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abort_debug(struct trapframe *tf, u_int fsr, u_int prefetch, u_int usermode,
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u_int far)
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{
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if (usermode) {
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struct thread *td;
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td = curthread;
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call_trapsignal(td, SIGTRAP, TRAP_BRKPT, far);
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userret(td, tf);
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} else {
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#ifdef KDB
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kdb_trap(T_BREAKPOINT, 0, tf);
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#else
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printf("No debugger in kernel.\n");
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#endif
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}
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}
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/*
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* Abort handler.
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*
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* FAR, FSR, and everything what can be lost after enabling
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* interrupts must be grabbed before the interrupts will be
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* enabled. Note that when interrupts will be enabled, we
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* could even migrate to another CPU ...
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*
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* TODO: move quick cases to ASM
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*/
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void
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abort_handler(struct trapframe *tf, int prefetch)
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{
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struct thread *td;
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vm_offset_t far, va;
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int idx, usermode;
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uint32_t fsr;
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struct ksig ksig;
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struct proc *p;
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struct pcb *pcb;
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struct vm_map *map;
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struct vmspace *vm;
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vm_prot_t ftype;
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int rv;
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#ifdef INVARIANTS
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void *onfault;
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#endif
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td = curthread;
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fsr = (prefetch) ? cp15_ifsr_get(): cp15_dfsr_get();
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far = (prefetch) ? TRAPF_PC(tf) : cp15_dfar_get();
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idx = FSR_TO_FAULT(fsr);
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usermode = TRAPF_USERMODE(tf); /* Abort came from user mode? */
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if (usermode)
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td->td_frame = tf;
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CTR4(KTR_TRAP, "abort_handler: fsr %#x (idx %u) far %#x prefetch %u",
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fsr, idx, far, prefetch);
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/*
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* Firstly, handle aborts that are not directly related to mapping.
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*/
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if (__predict_false(idx == FAULT_EA_IMPREC)) {
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abort_imprecise(tf, fsr, prefetch, usermode);
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return;
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}
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if (__predict_false(idx == FAULT_DEBUG)) {
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abort_debug(tf, fsr, prefetch, usermode, far);
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return;
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}
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#ifdef ARM_NEW_PMAP
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rv = pmap_fault(PCPU_GET(curpmap), far, fsr, idx, usermode);
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if (rv == 0) {
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return;
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} else if (rv == EFAULT) {
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call_trapsignal(td, SIGSEGV, SEGV_MAPERR, far);
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userret(td, tf);
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return;
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}
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#endif
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/*
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* Now, when we handled imprecise and debug aborts, the rest of
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* aborts should be really related to mapping.
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*
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*/
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PCPU_INC(cnt.v_trap);
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#ifdef KDB
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if (kdb_active) {
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kdb_reenter();
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goto out;
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}
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#endif
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if (__predict_false((td->td_pflags & TDP_NOFAULTING) != 0)) {
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/*
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* Due to both processor errata and lazy TLB invalidation when
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* access restrictions are removed from virtual pages, memory
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* accesses that are allowed by the physical mapping layer may
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* nonetheless cause one spurious page fault per virtual page.
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* When the thread is executing a "no faulting" section that
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* is bracketed by vm_fault_{disable,enable}_pagefaults(),
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* every page fault is treated as a spurious page fault,
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* unless it accesses the same virtual address as the most
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* recent page fault within the same "no faulting" section.
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*/
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if (td->td_md.md_spurflt_addr != far ||
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(td->td_pflags & TDP_RESETSPUR) != 0) {
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td->td_md.md_spurflt_addr = far;
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td->td_pflags &= ~TDP_RESETSPUR;
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tlb_flush_local(far & ~PAGE_MASK);
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return;
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}
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} else {
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/*
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* If we get a page fault while in a critical section, then
|
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* it is most likely a fatal kernel page fault. The kernel
|
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* is already going to panic trying to get a sleep lock to
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* do the VM lookup, so just consider it a fatal trap so the
|
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* kernel can print out a useful trap message and even get
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* to the debugger.
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*
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* If we get a page fault while holding a non-sleepable
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* lock, then it is most likely a fatal kernel page fault.
|
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* If WITNESS is enabled, then it's going to whine about
|
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* bogus LORs with various VM locks, so just skip to the
|
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* fatal trap handling directly.
|
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*/
|
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if (td->td_critnest != 0 ||
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WITNESS_CHECK(WARN_SLEEPOK | WARN_GIANTOK, NULL,
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"Kernel page fault") != 0) {
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abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig);
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return;
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}
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}
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|
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/* Re-enable interrupts if they were enabled previously. */
|
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if (td->td_md.md_spinlock_count == 0) {
|
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if (__predict_true(tf->tf_spsr & PSR_I) == 0)
|
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enable_interrupts(PSR_I);
|
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if (__predict_true(tf->tf_spsr & PSR_F) == 0)
|
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enable_interrupts(PSR_F);
|
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}
|
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|
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p = td->td_proc;
|
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if (usermode) {
|
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td->td_pticks = 0;
|
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if (td->td_ucred != p->p_ucred)
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cred_update_thread(td);
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}
|
||||
|
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/* Invoke the appropriate handler, if necessary. */
|
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if (__predict_false(aborts[idx].func != NULL)) {
|
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if ((aborts[idx].func)(tf, idx, fsr, far, prefetch, td, &ksig))
|
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goto do_trapsignal;
|
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goto out;
|
||||
}
|
||||
|
||||
/*
|
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* At this point, we're dealing with one of the following aborts:
|
||||
*
|
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* FAULT_TRAN_xx - Translation
|
||||
* FAULT_PERM_xx - Permission
|
||||
*
|
||||
* These are the main virtual memory-related faults signalled by
|
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* the MMU.
|
||||
*/
|
||||
|
||||
/* fusubailout is used by [fs]uswintr to avoid page faulting */
|
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pcb = td->td_pcb;
|
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if (__predict_false(pcb->pcb_onfault == fusubailout)) {
|
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tf->tf_r0 = EFAULT;
|
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tf->tf_pc = (register_t)pcb->pcb_onfault;
|
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return;
|
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}
|
||||
|
||||
/*
|
||||
* QQQ: ARM has a set of unprivileged load and store instructions
|
||||
* (LDRT/LDRBT/STRT/STRBT ...) which are supposed to be used
|
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* in other than user mode and OS should recognize their
|
||||
* aborts and behaved appropriately. However, there is no way
|
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* how to do that reasonably in general unless we restrict
|
||||
* the handling somehow. One way is to limit the handling for
|
||||
* aborts which come from undefined mode only.
|
||||
*
|
||||
* Anyhow, we do not use these instructions and do not implement
|
||||
* any special handling for them.
|
||||
*/
|
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|
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va = trunc_page(far);
|
||||
if (va >= KERNBASE) {
|
||||
/*
|
||||
* Don't allow user-mode faults in kernel address space.
|
||||
*/
|
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if (usermode)
|
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goto nogo;
|
||||
|
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map = kernel_map;
|
||||
} else {
|
||||
/*
|
||||
* This is a fault on non-kernel virtual memory. If curproc
|
||||
* is NULL or curproc->p_vmspace is NULL the fault is fatal.
|
||||
*/
|
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vm = (p != NULL) ? p->p_vmspace : NULL;
|
||||
if (vm == NULL)
|
||||
goto nogo;
|
||||
|
||||
map = &vm->vm_map;
|
||||
if (!usermode && (td->td_intr_nesting_level != 0 ||
|
||||
pcb->pcb_onfault == NULL)) {
|
||||
abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
ftype = (fsr & FSR_WNR) ? VM_PROT_WRITE : VM_PROT_READ;
|
||||
if (prefetch)
|
||||
ftype |= VM_PROT_EXECUTE;
|
||||
|
||||
#ifndef ARM_NEW_PMAP
|
||||
if (pmap_fault_fixup(vmspace_pmap(td->td_proc->p_vmspace), va, ftype,
|
||||
usermode)) {
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef INVARIANTS
|
||||
onfault = pcb->pcb_onfault;
|
||||
pcb->pcb_onfault = NULL;
|
||||
#endif
|
||||
if (map != kernel_map) {
|
||||
/*
|
||||
* Keep swapout from messing with us during this
|
||||
* critical time.
|
||||
*/
|
||||
PROC_LOCK(p);
|
||||
++p->p_lock;
|
||||
PROC_UNLOCK(p);
|
||||
|
||||
/* Fault in the user page: */
|
||||
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
|
||||
|
||||
PROC_LOCK(p);
|
||||
--p->p_lock;
|
||||
PROC_UNLOCK(p);
|
||||
} else {
|
||||
/*
|
||||
* Don't have to worry about process locking or stacks in the
|
||||
* kernel.
|
||||
*/
|
||||
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
|
||||
}
|
||||
|
||||
#ifdef INVARIANTS
|
||||
pcb->pcb_onfault = onfault;
|
||||
#endif
|
||||
|
||||
if (__predict_true(rv == KERN_SUCCESS))
|
||||
goto out;
|
||||
nogo:
|
||||
if (!usermode) {
|
||||
if (td->td_intr_nesting_level == 0 &&
|
||||
pcb->pcb_onfault != NULL) {
|
||||
tf->tf_r0 = rv;
|
||||
tf->tf_pc = (int)pcb->pcb_onfault;
|
||||
return;
|
||||
}
|
||||
CTR2(KTR_TRAP, "%s: vm_fault() failed with %d", __func__, rv);
|
||||
abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig);
|
||||
return;
|
||||
}
|
||||
|
||||
ksig.sig = (rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV;
|
||||
ksig.code = 0;
|
||||
ksig.addr = far;
|
||||
|
||||
do_trapsignal:
|
||||
call_trapsignal(td, ksig.sig, ksig.code, ksig.addr);
|
||||
out:
|
||||
if (usermode)
|
||||
userret(td, tf);
|
||||
}
|
||||
|
||||
/*
|
||||
* abort_fatal() handles the following data aborts:
|
||||
|
||||
* FAULT_DEBUG - Debug Event
|
||||
* FAULT_ACCESS_xx - Acces Bit
|
||||
* FAULT_EA_PREC - Precise External Abort
|
||||
* FAULT_DOMAIN_xx - Domain Fault
|
||||
* FAULT_EA_TRAN_xx - External Translation Abort
|
||||
* FAULT_EA_IMPREC - Imprecise External Abort
|
||||
* + all undefined codes for ABORT
|
||||
*
|
||||
* We should never see these on a properly functioning system.
|
||||
*
|
||||
* This function is also called by the other handlers if they
|
||||
* detect a fatal problem.
|
||||
*
|
||||
* Note: If 'l' is NULL, we assume we're dealing with a prefetch abort.
|
||||
*/
|
||||
static int
|
||||
abort_fatal(struct trapframe *tf, u_int idx, u_int fsr, u_int far, u_int prefetch,
|
||||
struct thread *td, struct ksig *ksig)
|
||||
{
|
||||
u_int usermode;
|
||||
const char *mode;
|
||||
const char *rw_mode;
|
||||
|
||||
usermode = TRAPF_USERMODE(tf);
|
||||
mode = usermode ? "user" : "kernel";
|
||||
rw_mode = fsr & FSR_WNR ? "write" : "read";
|
||||
disable_interrupts(PSR_I|PSR_F);
|
||||
|
||||
if (td != NULL) {
|
||||
printf("Fatal %s mode data abort: '%s' on %s\n", mode,
|
||||
aborts[idx].desc, rw_mode);
|
||||
printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr);
|
||||
if (idx != FAULT_EA_IMPREC)
|
||||
printf("%08x, ", far);
|
||||
else
|
||||
printf("Invalid, ");
|
||||
printf("spsr=%08x\n", tf->tf_spsr);
|
||||
} else {
|
||||
printf("Fatal %s mode prefetch abort at 0x%08x\n",
|
||||
mode, tf->tf_pc);
|
||||
printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr);
|
||||
}
|
||||
|
||||
printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n",
|
||||
tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3);
|
||||
printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n",
|
||||
tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7);
|
||||
printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n",
|
||||
tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11);
|
||||
printf("r12=%08x, ", tf->tf_r12);
|
||||
|
||||
if (usermode)
|
||||
printf("usp=%08x, ulr=%08x",
|
||||
tf->tf_usr_sp, tf->tf_usr_lr);
|
||||
else
|
||||
printf("ssp=%08x, slr=%08x",
|
||||
tf->tf_svc_sp, tf->tf_svc_lr);
|
||||
printf(", pc =%08x\n\n", tf->tf_pc);
|
||||
|
||||
#ifdef KDB
|
||||
if (debugger_on_panic || kdb_active)
|
||||
kdb_trap(fsr, 0, tf);
|
||||
#endif
|
||||
panic("Fatal abort");
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
||||
/*
|
||||
* abort_align() handles the following data abort:
|
||||
*
|
||||
* FAULT_ALIGN - Alignment fault
|
||||
*
|
||||
* Every memory access should be correctly aligned in kernel including
|
||||
* user to kernel and vice versa data copying, so we ignore pcb_onfault,
|
||||
* and it's always fatal. We generate a signal in case of abort from user mode.
|
||||
*/
|
||||
static int
|
||||
abort_align(struct trapframe *tf, u_int idx, u_int fsr, u_int far, u_int prefetch,
|
||||
struct thread *td, struct ksig *ksig)
|
||||
{
|
||||
u_int usermode;
|
||||
|
||||
usermode = TRAPF_USERMODE(tf);
|
||||
|
||||
/*
|
||||
* Alignment faults are always fatal if they occur in any but user mode.
|
||||
*
|
||||
* XXX The old trap code handles pcb fault even for alignment traps.
|
||||
* Unfortunately, we don't known why and if is this need.
|
||||
*/
|
||||
if (!usermode) {
|
||||
if (td->td_intr_nesting_level == 0 && td != NULL &&
|
||||
td->td_pcb->pcb_onfault != NULL) {
|
||||
printf("%s: Got alignment fault with pcb_onfault set"
|
||||
", please report this issue\n", __func__);
|
||||
tf->tf_r0 = EFAULT;;
|
||||
tf->tf_pc = (int)td->td_pcb->pcb_onfault;
|
||||
return (0);
|
||||
}
|
||||
abort_fatal(tf, idx, fsr, far, prefetch, td, ksig);
|
||||
}
|
||||
/* Deliver a bus error signal to the process */
|
||||
ksig->code = 0;
|
||||
ksig->sig = SIGBUS;
|
||||
ksig->addr = far;
|
||||
return (1);
|
||||
}
|
||||
|
||||
/*
|
||||
* abort_icache() handles the following data abort:
|
||||
*
|
||||
* FAULT_ICACHE - Instruction cache maintenance
|
||||
*
|
||||
* According to manual, FAULT_ICACHE is translation fault during cache
|
||||
* maintenance operation. In fact, no cache maintenance operation on
|
||||
* not mapped virtual addresses should be called. As cache maintenance
|
||||
* operation (except DMB, DSB, and Flush Prefetch Buffer) are priviledged,
|
||||
* the abort is concider as fatal for now. However, all the matter with
|
||||
* cache maintenance operation on virtual addresses could be really complex
|
||||
* and fuzzy in SMP case, so maybe in future standard fault mechanism
|
||||
* should be held here including vm_fault() calling.
|
||||
*/
|
||||
static int
|
||||
abort_icache(struct trapframe *tf, u_int idx, u_int fsr, u_int far, u_int prefetch,
|
||||
struct thread *td, struct ksig *ksig)
|
||||
{
|
||||
abort_fatal(tf, idx, fsr, far, prefetch, td, ksig);
|
||||
return(0);
|
||||
}
|
||||
@ -41,6 +41,8 @@
|
||||
#ifndef MACHINE_ARMREG_H
|
||||
#define MACHINE_ARMREG_H
|
||||
|
||||
#include <machine/acle-compat.h>
|
||||
|
||||
#define INSN_SIZE 4
|
||||
#define INSN_COND_MASK 0xf0000000 /* Condition mask */
|
||||
#define PSR_MODE 0x0000001f /* mode mask */
|
||||
@ -351,10 +353,10 @@
|
||||
#define CACHE_UNI_CACHE 4
|
||||
|
||||
/* Fault status register definitions */
|
||||
|
||||
#define FAULT_TYPE_MASK 0x0f
|
||||
#define FAULT_USER 0x10
|
||||
|
||||
#if __ARM_ARCH < 6
|
||||
#define FAULT_TYPE_MASK 0x0f
|
||||
#define FAULT_WRTBUF_0 0x00 /* Vector Exception */
|
||||
#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
|
||||
#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
|
||||
@ -377,14 +379,36 @@
|
||||
#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */
|
||||
#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */
|
||||
|
||||
/* Fault status register definitions - v6+ */
|
||||
#define FSR_STATUS_TO_IDX(fsr) (((fsr) & 0xF) | \
|
||||
(((fsr) & (1 << 10)>> (10 - 4))))
|
||||
#define FSR_LPAE (1 << 9) /* LPAE indicator */
|
||||
#define FSR_WNR (1 << 11) /* Write-not-Read access */
|
||||
#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
|
||||
#define FSR_CM (1 << 13) /* Cache maintenance fault */
|
||||
#else /* __ARM_ARCH < 6 */
|
||||
|
||||
#define FAULT_ALIGN 0x001 /* Alignment Fault */
|
||||
#define FAULT_DEBUG 0x002 /* Debug Event */
|
||||
#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */
|
||||
#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */
|
||||
#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */
|
||||
#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */
|
||||
#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */
|
||||
#define FAULT_EA_PREC 0x008 /* External Abort */
|
||||
#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */
|
||||
#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */
|
||||
#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */
|
||||
#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */
|
||||
#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */
|
||||
#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */
|
||||
#define FAULT_TLB_CONFLICT 0x010 /* Permission Fault (L2) */
|
||||
#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */
|
||||
#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */
|
||||
#define FAULT_PARITY 0x019 /* Parity Error */
|
||||
#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */
|
||||
#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */
|
||||
|
||||
#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \
|
||||
((((fsr) & (1 << 10)) >> (10 - 4))))
|
||||
#define FSR_LPAE (1 << 9) /* LPAE indicator */
|
||||
#define FSR_WNR (1 << 11) /* Write-not-Read access */
|
||||
#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
|
||||
#define FSR_CM (1 << 13) /* Cache maintenance fault */
|
||||
#endif /* !__ARM_ARCH < 6 */
|
||||
|
||||
/*
|
||||
* Address of the vector page, low and high versions.
|
||||
|
||||
@ -48,6 +48,7 @@ struct md_utrap {
|
||||
struct mdthread {
|
||||
int md_spinlock_count; /* (k) */
|
||||
register_t md_saved_cspr; /* (k) */
|
||||
register_t md_spurflt_addr; /* (k) Spurious page fault address. */
|
||||
int md_ptrace_instr;
|
||||
int md_ptrace_addr;
|
||||
register_t md_tp;
|
||||
|
||||
@ -53,7 +53,8 @@ arm/arm/support.S standard
|
||||
arm/arm/swtch.S standard
|
||||
arm/arm/sys_machdep.c standard
|
||||
arm/arm/syscall.c standard
|
||||
arm/arm/trap.c standard
|
||||
arm/arm/trap.c optional !armv6
|
||||
arm/arm/trap-v6.c optional armv6
|
||||
arm/arm/uio_machdep.c standard
|
||||
arm/arm/undefined.c standard
|
||||
arm/arm/vm_machdep.c standard
|
||||
|
||||
Loading…
Reference in New Issue
Block a user