Fix a bug in the ste_setmulti() routine. The NIC has 4 16-bit multicast
hash registers, not 2 32-bit ones. This would prevent the multicasr filter from being programmed correctly in some cases.
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@ -583,8 +583,10 @@ static void ste_setmulti(sc)
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}
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/* first, zot all the existing hash bits */
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CSR_WRITE_4(sc, STE_MAR0, 0);
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CSR_WRITE_4(sc, STE_MAR1, 0);
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CSR_WRITE_2(sc, STE_MAR0, 0);
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CSR_WRITE_2(sc, STE_MAR1, 0);
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CSR_WRITE_2(sc, STE_MAR2, 0);
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CSR_WRITE_2(sc, STE_MAR3, 0);
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/* now program new ones */
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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@ -597,8 +599,10 @@ static void ste_setmulti(sc)
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hashes[1] |= (1 << (h - 32));
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}
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CSR_WRITE_4(sc, STE_MAR0, hashes[0]);
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CSR_WRITE_4(sc, STE_MAR1, hashes[1]);
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CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
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CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
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CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
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CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
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STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
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STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
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@ -88,7 +88,9 @@
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#define STE_TX_RECLAIM_THRESH 0x5D
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#define STE_PHYCTL 0x5E
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#define STE_MAR0 0x60
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#define STE_MAR1 0x64
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#define STE_MAR1 0x62
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#define STE_MAR2 0x64
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#define STE_MAR3 0x66
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#define STE_STATS 0x68
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#define STE_DMACTL_RXDMA_STOPPED 0x00000001
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