Improve fix in r304629 by allowing configuration of the behaviour
through a SYSCTL instead of a compile time define. Add quirk by default for all LynxPoint XHCI controllers. PR: 227602 MFC after: 3 days Sponsored by: Mellanox Technologies
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@ -100,6 +100,7 @@ static int xhcidebug;
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static int xhciroute;
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static int xhcipolling;
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static int xhcidma32;
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static int xhcictlstep;
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SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
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&xhcidebug, 0, "Debug level");
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@ -109,9 +110,12 @@ SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
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&xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
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SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
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&xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
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SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
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&xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
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#else
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#define xhciroute 0
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#define xhcidma32 0
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#define xhcictlstep 0
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#endif
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#define XHCI_INTR_ENDPT 1
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@ -2240,11 +2244,17 @@ xhci_setup_generic_chain(struct usb_xfer *xfer)
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* Send a DATA1 message and invert the current
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* endpoint direction.
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*/
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#ifdef XHCI_STEP_STATUS_STAGE
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temp.step_td = (xfer->nframes != 0);
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#else
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temp.step_td = 0;
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#endif
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if (xhcictlstep || temp.sc->sc_ctlstep) {
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/*
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* Some XHCI controllers will not delay the
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* status stage until the next SOF. Force this
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* behaviour to avoid failed control
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* transfers.
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*/
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temp.step_td = (xfer->nframes != 0);
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} else {
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temp.step_td = 0;
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}
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temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
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temp.len = 0;
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temp.pc = NULL;
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@ -509,6 +509,8 @@ struct xhci_softc {
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uint8_t sc_noport;
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/* root HUB device configuration */
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uint8_t sc_conf;
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/* step status stage of all control transfers */
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uint8_t sc_ctlstep;
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/* root HUB port event bitmap, max 256 ports */
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uint8_t sc_hub_idata[32];
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@ -256,6 +256,7 @@ xhci_pci_attach(device_t self)
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*/
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sc->sc_port_route = &xhci_pci_port_route;
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sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
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sc->sc_ctlstep = 1;
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break;
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}
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