Add platform support for QorIQ SoCs.
This includes the following changes: * SMP kickoff for QorIQ (tested on P5020) * Errata fixes for some silicon revisions * Enables L2 (and L3 if available) caches Obtained from: Semihalf Sponsored by: Alex Perez/Inertial Computing
This commit is contained in:
jhibbits
parent
95fd2c39d8
commit
0ecd3402cf
@ -316,8 +316,20 @@ booke_init(uint32_t arg1, uint32_t arg2)
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ret = powerpc_init(dtbp, 0, 0, mdp);
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/* Enable L1 caches */
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/* Default to 32 byte cache line size. */
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switch ((mfpvr()) >> 16) {
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case FSL_E500mc:
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case FSL_E5500:
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case FSL_E6500:
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cacheline_size = 64;
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break;
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}
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/* Enable caches */
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booke_enable_l1_cache();
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booke_enable_l2_cache();
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booke_enable_bpred();
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return (ret);
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}
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@ -301,7 +301,7 @@ bp_ntlb1s:
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.globl bp_tlb1
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bp_tlb1:
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.space 4 * 3 * 16
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.space 4 * 3 * 64
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.globl bp_tlb1_end
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bp_tlb1_end:
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@ -730,6 +730,113 @@ ENTRY(icache_enable)
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isync
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blr
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/*
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* L2 cache disable/enable/inval sequences for E500mc.
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*/
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ENTRY(l2cache_inval)
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mfspr %r3, SPR_L2CSR0
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oris %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
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ori %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@l
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isync
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mtspr SPR_L2CSR0, %r3
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isync
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1: mfspr %r3, SPR_L2CSR0
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andis. %r3, %r3, L2CSR0_L2FI@h
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bne 1b
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blr
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ENTRY(l2cache_enable)
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mfspr %r3, SPR_L2CSR0
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oris %r3, %r3, (L2CSR0_L2E | L2CSR0_L2PE)@h
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isync
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mtspr SPR_L2CSR0, %r3
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isync
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blr
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/*
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* Branch predictor setup.
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*/
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ENTRY(bpred_enable)
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mfspr %r3, SPR_BUCSR
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ori %r3, %r3, BUCSR_BBFI
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isync
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mtspr SPR_BUCSR, %r3
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isync
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ori %r3, %r3, BUCSR_BPEN
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isync
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mtspr SPR_BUCSR, %r3
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isync
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blr
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ENTRY(dataloss_erratum_access)
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/* Lock two cache lines into I-Cache */
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sync
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mfspr %r11, SPR_L1CSR1
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rlwinm %r11, %r11, 0, ~L1CSR1_ICUL
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sync
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isync
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mtspr SPR_L1CSR1, %r11
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isync
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mflr %r9
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bl 1f
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.long 2f-.
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1:
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mflr %r5
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lwz %r8, 0(%r5)
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mtlr %r9
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add %r8, %r8, %r5
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icbtls 0, 0, %r8
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addi %r9, %r8, 64
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sync
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mfspr %r11, SPR_L1CSR1
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3: andi. %r11, %r11, L1CSR1_ICUL
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bne 3b
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icbtls 0, 0, %r9
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sync
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mfspr %r11, SPR_L1CSR1
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3: andi. %r11, %r11, L1CSR1_ICUL
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bne 3b
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b 2f
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.align 6
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/* Inside a locked cacheline, wait a while, write, then wait a while */
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2: sync
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mfspr %r5, TBR_TBL
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4: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */
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mfspr %r5, TBR_TBL
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subf. %r5, %r5, %r11
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bgt 4b
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stw %r4, 0(%r3)
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mfspr %r5, TBR_TBL
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4: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */
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mfspr %r5, TBR_TBL
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subf. %r5, %r5, %r11
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bgt 4b
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sync
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/*
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* Fill out the rest of this cache line and the next with nops,
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* to ensure that nothing outside the locked area will be
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* fetched due to a branch.
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*/
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.rept 19
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nop
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.endr
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icblc 0, 0, %r8
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icblc 0, 0, %r9
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blr
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/*
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* int setfault()
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*
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@ -27,9 +27,15 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/machdep.h>
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#include <dev/fdt/fdt_common.h>
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@ -42,6 +48,7 @@ extern void icache_enable(void);
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extern void icache_inval(void);
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extern void l2cache_enable(void);
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extern void l2cache_inval(void);
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extern void bpred_enable(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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@ -79,7 +86,6 @@ booke_enable_l1_cache(void)
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(csr & L1CSR1_ICE) ? "en" : "dis");
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}
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#if 0
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void
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booke_enable_l2_cache(void)
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{
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@ -102,55 +108,18 @@ booke_enable_l2_cache(void)
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}
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void
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booke_enable_l3_cache(void)
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booke_enable_bpred(void)
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{
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uint32_t csr, size, ver;
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uint32_t csr;
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/* Enable L3 CoreNet Platform Cache (CPC) */
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
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ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
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l3cache_inval();
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l3cache_enable();
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}
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((boothowto & RB_VERBOSE) != 0 ||
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(csr & OCP85XX_CPC_CSR0_CE) == 0) {
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size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
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printf("L3 Corenet Platform Cache: %d KB %sabled\n",
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size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
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"dis" : "en");
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}
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}
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bpred_enable();
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csr = mfspr(SPR_BUCSR);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
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printf("Branch Predictor %sabled\n",
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(csr & BUCSR_BPEN) ? "en" : "dis");
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}
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void
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booke_disable_l2_cache(void)
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{
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}
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static void
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l3cache_inval(void)
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{
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/* Flash invalidate the CPC and clear all the locks */
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC);
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while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC))
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;
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}
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static void
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l3cache_enable(void)
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{
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
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OCP85XX_CPC_CSR0_PE);
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/* Read back to sync write */
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ccsr_read4(OCP85XX_CPC_CSR0);
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}
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#endif
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@ -32,18 +32,26 @@ __FBSDID("$FreeBSD$");
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/reboot.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/machdep.h>
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#include <machine/pio.h>
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#include <machine/spr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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@ -249,3 +257,166 @@ law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
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return (rv);
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}
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static void
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l3cache_inval(void)
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{
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/* Flash invalidate the CPC and clear all the locks */
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC);
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while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC))
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;
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}
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static void
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l3cache_enable(void)
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{
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
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OCP85XX_CPC_CSR0_PE);
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/* Read back to sync write */
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ccsr_read4(OCP85XX_CPC_CSR0);
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}
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void
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mpc85xx_enable_l3_cache(void)
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{
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uint32_t csr, size, ver;
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/* Enable L3 CoreNet Platform Cache (CPC) */
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
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ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
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l3cache_inval();
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l3cache_enable();
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}
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((boothowto & RB_VERBOSE) != 0 ||
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(csr & OCP85XX_CPC_CSR0_CE) == 0) {
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size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
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printf("L3 Corenet Platform Cache: %d KB %sabled\n",
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size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
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"dis" : "en");
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}
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}
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}
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static void
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mpc85xx_dataloss_erratum_spr976(void)
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{
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uint32_t svr = SVR_VER(mfspr(SPR_SVR));
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/* Ignore whether it's the E variant */
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svr &= ~0x8;
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if (svr != SVR_P3041 && svr != SVR_P4040 &&
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svr != SVR_P4080 && svr != SVR_P5020)
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return;
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mb();
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isync();
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mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
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isync();
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}
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static vm_offset_t
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mpc85xx_map_dcsr(void)
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{
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phandle_t node;
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u_long b, s;
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int err;
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/*
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* Try to access the dcsr node directly i.e. through /aliases/.
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*/
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if ((node = OF_finddevice("dcsr")) != -1)
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if (fdt_is_compatible_strict(node, "fsl,dcsr"))
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goto moveon;
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/*
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* Find the node the long way.
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*/
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if ((node = OF_finddevice("/")) == -1)
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return (ENXIO);
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if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
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return (ENXIO);
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moveon:
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err = fdt_get_range(node, 0, &b, &s);
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if (err != 0)
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return (err);
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#ifdef QORIQ_DPAA
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law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
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#endif
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return pmap_early_io_map(b, 0x400000);
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}
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void
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mpc85xx_fix_errata(vm_offset_t va_ccsr)
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{
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uint32_t svr = SVR_VER(mfspr(SPR_SVR));
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vm_offset_t va_dcsr;
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/* Ignore whether it's the E variant */
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svr &= ~0x8;
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if (svr != SVR_P3041 && svr != SVR_P4040 &&
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svr != SVR_P4080 && svr != SVR_P5020)
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return;
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if (mfmsr() & PSL_EE)
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return;
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/*
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* dcsr region need to be mapped thus patch can refer to.
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* Align dcsr right after ccsbar.
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*/
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va_dcsr = mpc85xx_map_dcsr();
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if (va_dcsr == 0)
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goto err;
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/*
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* As A004510 errata specify, special purpose register 976
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* SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
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* does not document SPR976 register.
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*/
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mpc85xx_dataloss_erratum_spr976();
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/*
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* Specific settings in the CCF and core platform cache (CPC)
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* are required to reconfigure the CoreNet coherency fabric.
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* The register settings that should be updated are described
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* in errata and relay on base address, offset and updated value.
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* Special conditions must be used to update these registers correctly.
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*/
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dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
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dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
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dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
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dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
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dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
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switch (svr) {
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case SVR_P5020:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
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break;
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case SVR_P4040:
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case SVR_P4080:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
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break;
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case SVR_P3041:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
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}
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dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
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dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
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err:
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return;
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}
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@ -40,6 +40,25 @@ extern vm_offset_t ccsrbar_va;
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#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
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#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
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#define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
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#define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
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#define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
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#define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
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#define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
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/*
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* Run Control and Power Management registers
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*/
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#define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
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#define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
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#define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
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/*
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* DDR Memory controller.
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*/
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#define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
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/*
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* E500 Coherency Module registers
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*/
|
||||
@ -68,6 +87,7 @@ extern vm_offset_t ccsrbar_va;
|
||||
#define OCP85XX_TGTIF_RAM1 0x10
|
||||
#define OCP85XX_TGTIF_RAM2 0x11
|
||||
#define OCP85XX_TGTIF_BMAN 0x18
|
||||
#define OCP85XX_TGTIF_DCSR 0x1D
|
||||
#define OCP85XX_TGTIF_QMAN 0x3C
|
||||
#define OCP85XX_TRGT_SHIFT 20
|
||||
#else
|
||||
@ -83,6 +103,20 @@ extern vm_offset_t ccsrbar_va;
|
||||
*/
|
||||
#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
|
||||
|
||||
/*
|
||||
* L3 CoreNet platform cache (CPC) registers
|
||||
*/
|
||||
#define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
|
||||
#define OCP85XX_CPC_CSR0_CE 0x80000000
|
||||
#define OCP85XX_CPC_CSR0_PE 0x40000000
|
||||
#define OCP85XX_CPC_CSR0_FI 0x00200000
|
||||
#define OCP85XX_CPC_CSR0_WT 0x00080000
|
||||
#define OCP85XX_CPC_CSR0_FL 0x00000800
|
||||
#define OCP85XX_CPC_CSR0_LFC 0x00000400
|
||||
#define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
|
||||
#define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
|
||||
#define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
|
||||
|
||||
/*
|
||||
* Power-On Reset configuration
|
||||
*/
|
||||
@ -110,4 +144,8 @@ int law_pci_target(struct resource *, int *, int *);
|
||||
DECLARE_CLASS(mpc85xx_platform);
|
||||
int mpc85xx_attach(platform_t);
|
||||
|
||||
void mpc85xx_enable_l3_cache(void);
|
||||
void mpc85xx_fix_errata(vm_offset_t);
|
||||
void dataloss_erratum_access(vm_offset_t, uint32_t);
|
||||
|
||||
#endif /* _MPC85XX_H_ */
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "opt_platform.h"
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
@ -38,6 +39,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <machine/bus.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/hid.h>
|
||||
#include <machine/machdep.h>
|
||||
#include <machine/platform.h>
|
||||
#include <machine/platformvar.h>
|
||||
#include <machine/smp.h>
|
||||
@ -175,6 +177,9 @@ mpc85xx_attach(platform_t plat)
|
||||
}
|
||||
ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
|
||||
|
||||
mpc85xx_fix_errata(ccsrbar_va);
|
||||
mpc85xx_enable_l3_cache();
|
||||
|
||||
/*
|
||||
* Clear local access windows. Skip DRAM entries, so we don't shoot
|
||||
* ourselves in the foot.
|
||||
@ -182,14 +187,14 @@ mpc85xx_attach(platform_t plat)
|
||||
law_max = law_getmax();
|
||||
for (i = 0; i < law_max; i++) {
|
||||
sr = ccsr_read4(OCP85XX_LAWSR(i));
|
||||
if ((sr & 0x80000000) == 0)
|
||||
if ((sr & OCP85XX_ENA_MASK) == 0)
|
||||
continue;
|
||||
tgt = (sr & 0x01f00000) >> 20;
|
||||
if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
|
||||
tgt == OCP85XX_TGTIF_RAM_INTL)
|
||||
continue;
|
||||
|
||||
ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
|
||||
ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK);
|
||||
}
|
||||
|
||||
return (0);
|
||||
@ -256,7 +261,11 @@ mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
|
||||
* HID0[SEL_TBCLK] = 0
|
||||
*/
|
||||
if (freq != 0)
|
||||
#ifdef QORIQ_DPAA
|
||||
ticks = freq / 32;
|
||||
#else
|
||||
ticks = freq / 8;
|
||||
#endif
|
||||
|
||||
out:
|
||||
if (ticks <= 0)
|
||||
@ -309,17 +318,37 @@ mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
|
||||
{
|
||||
#ifdef SMP
|
||||
uint32_t *tlb1;
|
||||
uint32_t bptr, eebpcr;
|
||||
vm_paddr_t bptr;
|
||||
uint32_t reg;
|
||||
int i, timeout;
|
||||
uintptr_t brr;
|
||||
int cpuid;
|
||||
|
||||
eebpcr = ccsr_read4(OCP85XX_EEBPCR);
|
||||
if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
|
||||
#ifdef QORIQ_DPAA
|
||||
uint32_t tgt;
|
||||
|
||||
reg = ccsr_read4(OCP85XX_COREDISR);
|
||||
cpuid = pc->pc_cpuid;
|
||||
|
||||
if ((reg & cpuid) != 0) {
|
||||
printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
brr = OCP85XX_BRR;
|
||||
#else /* QORIQ_DPAA */
|
||||
brr = OCP85XX_EEBPCR;
|
||||
cpuid = pc->pc_cpuid + 24;
|
||||
#endif
|
||||
reg = ccsr_read4(brr);
|
||||
if ((reg & (1 << cpuid)) != 0) {
|
||||
printf("SMP: CPU %d already out of hold-off state!\n",
|
||||
pc->pc_cpuid);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
ap_pcpu = pc;
|
||||
__asm __volatile("msync; isync");
|
||||
|
||||
i = 0;
|
||||
tlb1 = bp_tlb1;
|
||||
@ -335,24 +364,67 @@ mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
|
||||
if (i < bp_ntlb1s)
|
||||
bp_ntlb1s = i;
|
||||
|
||||
/* Flush caches to have our changes hit DRAM. */
|
||||
cpu_flush_dcache(__boot_page, 4096);
|
||||
|
||||
bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
|
||||
KASSERT((bptr & 0xfff) == 0,
|
||||
("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
|
||||
#ifdef QORIQ_DPAA
|
||||
|
||||
/*
|
||||
* Read DDR controller configuration to select proper BPTR target ID.
|
||||
*
|
||||
* On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
|
||||
* interleaving. If this bit is set, we have to use
|
||||
* OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
|
||||
* this bit is reserved and always 0.
|
||||
*/
|
||||
|
||||
reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
|
||||
if (reg & (1 << 29))
|
||||
tgt = OCP85XX_TGTIF_RAM_INTL;
|
||||
else
|
||||
tgt = OCP85XX_TGTIF_RAM1;
|
||||
|
||||
/*
|
||||
* Set BSTR to the physical address of the boot page
|
||||
*/
|
||||
ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
|
||||
ccsr_write4(OCP85XX_BSTRL, bptr);
|
||||
ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
|
||||
(tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2));
|
||||
|
||||
/* Read back OCP85XX_BSTAR to synchronize write */
|
||||
ccsr_read4(OCP85XX_BSTAR);
|
||||
|
||||
/*
|
||||
* Enable and configure time base on new CPU.
|
||||
*/
|
||||
|
||||
/* Set TB clock source to platform clock / 32 */
|
||||
reg = ccsr_read4(CCSR_CTBCKSELR);
|
||||
ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
|
||||
|
||||
/* Enable TB */
|
||||
reg = ccsr_read4(CCSR_CTBENR);
|
||||
ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
|
||||
#else
|
||||
|
||||
/*
|
||||
* Set BPTR to the physical address of the boot page
|
||||
*/
|
||||
bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
|
||||
KASSERT((bptr & 0xfff) == 0,
|
||||
("%s: boot page is not aligned (%#x)", __func__, bptr));
|
||||
bptr = (bptr >> 12) | 0x80000000u;
|
||||
ccsr_write4(OCP85XX_BPTR, bptr);
|
||||
__asm __volatile("isync; msync");
|
||||
|
||||
/* Flush caches to have our changes hit DRAM. */
|
||||
cpu_flush_dcache(__boot_page, 4096);
|
||||
#endif /* QORIQ_DPAA */
|
||||
|
||||
/*
|
||||
* Release AP from hold-off state
|
||||
*/
|
||||
eebpcr |= (1 << (pc->pc_cpuid + 24));
|
||||
ccsr_write4(OCP85XX_EEBPCR, eebpcr);
|
||||
reg = ccsr_read4(brr);
|
||||
ccsr_write4(brr, reg | (1 << cpuid));
|
||||
__asm __volatile("isync; msync");
|
||||
|
||||
timeout = 500;
|
||||
@ -364,7 +436,11 @@ mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
|
||||
* address (= 0xfffff000) isn't permanently remapped and thus not
|
||||
* usable otherwise.
|
||||
*/
|
||||
#ifdef QORIQ_DPAA
|
||||
ccsr_write4(OCP85XX_BSTAR, 0);
|
||||
#else
|
||||
ccsr_write4(OCP85XX_BPTR, 0);
|
||||
#endif
|
||||
__asm __volatile("isync; msync");
|
||||
|
||||
if (!pc->pc_awake)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user