Add support for the Atmel SAM9XE familiy of microcontrollers, which
consist of a ARM926EJ-S processor core with up to 512 Kbytes of on-chip flash. Tested with SAM9XE512.
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@ -90,7 +90,7 @@ static int
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at91pit_probe(device_t dev)
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{
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if (at91_is_sam9()) {
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if (at91_is_sam9() || at91_is_sam9xe()) {
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device_set_desc(dev, "AT91SAM9 PIT");
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return (0);
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}
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@ -71,7 +71,7 @@ static int
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at91_rst_probe(device_t dev)
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{
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if (at91_is_sam9()) {
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if (at91_is_sam9() || at91_is_sam9xe()) {
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device_set_desc(dev, "AT91SAM9 Reset Controller");
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return (0);
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}
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@ -64,7 +64,7 @@
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#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
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#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
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#define TWI_CWGR_DIV(rate) \
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(at91_is_sam9() ? \
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(at91_is_sam9() || at91_is_sam9xe() ? \
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((at91_master_clock / (4 * (rate))) - 3) : \
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((at91_master_clock / (4 * (rate))) - 2))
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@ -132,7 +132,7 @@ static int
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wdt_probe(device_t dev)
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{
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if (at91_is_sam9()) {
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if (at91_is_sam9() || at91_is_sam9xe()) {
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device_set_desc(dev, "WDT");
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return (0);
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}
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@ -61,6 +61,9 @@
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#define AT91_CPU_SAM9G10 0x819903a0
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#define AT91_CPU_SAM9G20 0x019905a0
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#define AT91_CPU_SAM9G45 0x819b05a0
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#define AT91_CPU_SAM9XE128 0x329973a0
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#define AT91_CPU_SAM9XE256 0x329a93a0
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#define AT91_CPU_SAM9XE512 0x329aa3a0
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#define AT91_ARCH(chipid) ((chipid >> 20) & 0xff)
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#define AT91_CPU(chipid) (chipid & ~AT91_CPU_VERSION_MASK)
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@ -197,21 +197,40 @@ static void
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at91_identify(driver_t *drv, device_t parent)
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{
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if (at91_cpu_is(AT91_CPU_SAM9260)) {
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switch (AT91_CPU(at91_chip_id)) {
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case AT91_CPU_SAM9260:
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case AT91_CPU_SAM9XE128:
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case AT91_CPU_SAM9XE256:
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case AT91_CPU_SAM9XE512:
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at91_add_child(parent, 0, "at91sam9260", 0, 0, 0, -1, 0, 0);
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at91_cpu_add_builtin_children(parent);
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break;
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}
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}
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static int
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at91_probe(device_t dev)
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{
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const char *desc;
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if (at91_cpu_is(AT91_CPU_SAM9260)) {
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device_set_desc(dev, "AT91SAM9260");
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return (0);
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switch (AT91_CPU(at91_chip_id)) {
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case AT91_CPU_SAM9260:
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desc = "AT91SAM9260";
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break;
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case AT91_CPU_SAM9XE128:
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desc = "AT91SAM9XE128";
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break;
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case AT91_CPU_SAM9XE256:
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desc = "AT91SAM9XE256";
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break;
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case AT91_CPU_SAM9XE512:
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desc = "AT91SAM9XE512";
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break;
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default:
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return (ENXIO);
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}
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return (ENXIO);
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device_set_desc(dev, desc);
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return (0);
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}
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static int
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@ -227,10 +246,6 @@ at91_attach(device_t dev)
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sc->sc_sh = at91sc->sc_sh;
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sc->dev = dev;
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/*
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* XXX These values work for the RM9200, SAM926[01], and SAM9260
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* will have to fix this when we want to support anything else. XXX
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*/
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_SYS_BASE,
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AT91SAM9260_SYS_SIZE, &sc->sc_sys_sh) != 0)
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panic("Enable to map system registers");
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@ -63,6 +63,7 @@ extern uint32_t at91_chip_id;
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static inline int at91_is_rm92(void);
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static inline int at91_is_sam9(void);
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static inline int at91_is_sam9xe(void);
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static inline int at91_cpu_is(u_int cpu);
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static inline int
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@ -79,6 +80,13 @@ at91_is_sam9(void)
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return (AT91_ARCH(at91_chip_id) == AT91_ARCH_SAM9);
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}
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static inline int
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at91_is_sam9xe(void)
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{
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return (AT91_ARCH(at91_chip_id) == AT91_ARCH_SAM9XE);
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}
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static inline int
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at91_cpu_is(u_int cpu)
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{
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@ -266,7 +266,7 @@ ate_attach(device_t dev)
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}
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/* New or old version, chooses buffer size. */
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sc->is_emacb = at91_is_sam9();
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sc->is_emacb = at91_is_sam9() || at91_is_sam9xe();
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sc->rx_buf_size = RX_BUF_SIZE(sc);
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err = ate_activate(dev);
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