Support following devices:
- on board 2nd CCU - Midori Elec. MDC-926Rs - Midori-Hayes ESP98 - NEC PC-9861K, PC-9801-101 PC-9801-120 - Melco IND-SP and IND-SS - PIO-9032A/B/C - B98-01 and B98-02 - IO-data device RSA-98II and RSA-98III - MC-16550 - MC-RS98 - Media Inteligent RSB-2000/3000 and RSB-384 - PCMCIA modem card Submitted by: Takahashi Yoshihiro <nyan@wyvern.cc.kogakuin.ac.jp>
This commit is contained in:
kato
parent
468764485d
commit
0f0d2d450c
@ -26,7 +26,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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* $Id: esp.h,v 1.3 1997/02/22 09:38:00 peter Exp $
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*/
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#ifndef _IC_ESP_H_
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@ -39,8 +39,13 @@
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/*
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* CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
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*/
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#ifdef PC98
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#define ESP_CMD1 0x400
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#define ESP_CMD2 0x500
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#else
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#define ESP_CMD1 4
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#define ESP_CMD2 5
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#endif
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/*
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* STAT1 and STAT2 are to get return values and status bytes;
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@ -59,6 +64,9 @@
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#define ESP_SETFLOWTYPE 0x08 /* set type of flow-control (2 bytes) */
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#define ESP_SETRXFLOW 0x0a /* set Rx FIFO flow control levels (4 bytes) */
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#define ESP_SETMODE 0x10 /* set board mode (1 byte) */
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#ifdef PC98
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#define ESP_SETCLOCK 0x23 /* set UART clock prescaler */
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#endif
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/* Mode bits (ESP_SETMODE). */
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#define ESP_MODE_FIFO 0x02 /* act like a 16550 (compatibility mode) */
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@ -31,25 +31,12 @@
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* SUCH DAMAGE.
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*
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* from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
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* $Id$
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* $Id: ns16550.h,v 1.5 1997/02/22 09:38:05 peter Exp $
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*/
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/*
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* NS16550 UART registers
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*/
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#ifdef PC98
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#define com_data 0x000 /* data register (R/W) */
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#define com_dlbl 0x000 /* divisor latch low (W) */
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#define com_dlbh 0x100 /* divisor latch high (W) */
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#define com_ier 0x100 /* interrupt enable (W) */
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#define com_iir 0x200 /* interrupt identification (R) */
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#define com_fifo 0x200 /* FIFO control (W) */
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#define com_lctl 0x300 /* line control register (R/W) */
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#define com_cfcr 0x300 /* line control register (R/W) */
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#define com_mcr 0x400 /* modem control register (R/W) */
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#define com_lsr 0x500 /* line status register (R/W) */
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#define com_msr 0x600 /* modem status register (R/W) */
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#else /* IBM-PC */
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#define com_data 0 /* data register (R/W) */
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#define com_dlbl 0 /* divisor latch low (W) */
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#define com_dlbh 1 /* divisor latch high (W) */
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@ -61,4 +48,108 @@
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#define com_mcr 4 /* modem control register (R/W) */
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#define com_lsr 5 /* line status register (R/W) */
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#define com_msr 6 /* modem status register (R/W) */
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#ifdef PC98
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#define com_emr com_msr /* Extension mode register for RSB-2000/3000. */
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/* I/O-DATA RSA Serise Exrension Register */
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#define rsa_msr 0 /* Mode Status Register (R/W) */
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#define rsa_ier 1 /* Interrupt Enable Register (R/W) */
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#define rsa_srr 2 /* Status Read Register (R) */
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#define rsa_frr 2 /* FIFO Reset Register (W) */
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#define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */
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#define rsa_tcr 4 /* Timer Control Register (W) */
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/*
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* RSA-98III RSA Mode Driver Data Sheet
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*
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* <<Register Map>>
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* Base + 0x00
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* Mode Select Register(Read/Write)
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* bit4=interrupt type(1: level, 0: edge)
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* bit3=Auto RTS-CTS Flow Control Enable
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* bit2=External FIFO Enable
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* bit1=Reserved(Default 0)Don't Change!!
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* bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
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*
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* Base + 0x01
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* Interrupt Enable Register(Read/Write)
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* bit4=Hardware Timer Interrupt Enable
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* bit3=Character Time-Out Interrupt Enable
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* bit2=Tx FIFO Empty Interrupt Enable
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* bit1=Tx FIFO Half Full Interrupt Enable
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* bit0=Rx FIFO Half Full Interrupt Enable
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*
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* Base + 0x02
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* Status Read Register(Read)
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* bit7=Hardware Time Out Interrupt Status(1: True, 0: False)
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* bit6=Character Time Out Interrupt Status
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* bit5=Rx FIFO Full Flag(0: True, 1: False)
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* bit4=Rx FIFO Half Full Flag
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* bit3=Rx FIFO Empty Flag
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* bit2=Tx FIFO Full Flag
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* bit1=Tx FIFO Half Full Flag
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* bit0=Tx FIFO Empty Flag
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*
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* Base + 0x02
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* FIFO Reset Register(Write)
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* Reset Extrnal FIFO
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*
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* Base + 0x03
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* Timer Interval Value Set Register(Read/Write)
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* Range of n: 1-255
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* Interval Value: n * 0.2ms
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*
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* Base + 0x04
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* Timer Control Register(Read/Write)
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* bit0=Timer Enable
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*
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* Base + 0x08 - 0x0f
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* Same as UART 16550
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*
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* Special Regisgter in RSA Mode
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* UART Data Register(Base + 0x08)
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* Data transfer between Extrnal FIFO
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*
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* UART MCR(Base + 0x0c)
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* bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer
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* bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer
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*
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* <<Intrrupt and Intrrupt Reset>>
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* o Reciver Line Status(from UART16550)
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* Reset: Read LSR
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*
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* o Modem Status(from UART16550)
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* Reset: Read MSR
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*
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* o Rx FIFO Half Full(from Extrnal FIFO)
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* Reset: Read Rx FIFO under Hall Full
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*
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* o Character Time Out(from Extrnal FIFO)
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* Reset: Read Rx FIFO or SRR
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*
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* o Tx FIFO Empty(from Extrnal FIFO)
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* Reset: Write Tx FIFO or Read SRR
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*
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* o Tx FIFO Half Full(from Extrnal FIFO)
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* Reset: Write Tx FIFO until Hall Full or Read SRR
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*
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* o Hardware Timer(from Extrnal FIFO)
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* Reset: Disable Timer in TCR
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* Notes: If you want to use Timer for next intrrupt,
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* you must enable Timer in TCR
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*
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* <<Used Setting>>
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* Auto RTS-CTS: Enable or Disable
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* External FIFO: Enable
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* Swap 8bytes: Disable
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* Haredware Timer: Disable
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* interrupt type: edge
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* interrupt source:
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* Hareware Timer
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* Character Time Out
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* Tx FIFO Empty
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* Rx FIFO Half Full
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*
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*/
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#endif /* PC98 */
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@ -31,12 +31,15 @@
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* SUCH DAMAGE.
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*
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* from: @(#)comreg.h 7.2 (Berkeley) 5/9/91
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* $Id: sioreg.h,v 1.9 1997/06/04 04:52:40 pst Exp $
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* $Id: sioreg.h,v 1.10 1997/06/04 16:25:15 pst Exp $
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*/
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/* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */
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#define COMBRD(x) (1843200 / (16*(x)))
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#ifdef PC98
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#define COMBRD_RSA(x) (14745600 / (16*(x)))
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#endif
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/* interrupt enable register */
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#define IER_ERXRDY 0x1
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@ -106,6 +109,16 @@
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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#ifdef PC98
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/* Hardware extension mode register for RSB-2000/3000. */
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#define EMR_EXBUFF 0x04
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#define EMR_CTSFLW 0x08
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#define EMR_DSRFLW 0x10
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#define EMR_RTSFLW 0x20
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#define EMR_DTRFLW 0x40
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#define EMR_EFMODE 0x80
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#endif
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/* speed to initialize to during chip tests */
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#define SIO_TEST_SPEED 9600
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@ -1,4 +1,4 @@
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# $Id: Makefile,v 1.19 1998/09/15 14:08:34 kato Exp $
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# $Id: Makefile,v 1.20 1998/11/23 07:34:37 kato Exp $
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#
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PROG= boot
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@ -16,7 +16,8 @@ CFLAGS+= ${CWARNFLAGS}
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# By default, if a serial port is going to be used as console, use COM1
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# (aka /dev/ttyd0).
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BOOT_COMCONSOLE_PORT?=0x30
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#BOOT_COMCONSOLE_PORT?=0x30
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BOOT_COMCONSOLE_PORT?=0x238
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BOOT_COMCONSOLE_CLK?=16
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BOOT_COMCONSOLE_MODE=0x0c
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CFLAGS+= -DCOMCONSOLE=${BOOT_COMCONSOLE_PORT} \
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@ -24,8 +25,8 @@ CFLAGS+= -DCOMCONSOLE=${BOOT_COMCONSOLE_PORT} \
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-DCOMCONSOLE_MODE=${BOOT_COMCONSOLE_MODE}
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# feature not implemented
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# BOOT_COMCONSOLE_SPEED?=9600
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# CFLAGS+= -DCONSPEED=${BOOT_COMCONSOLE_SPEED}
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BOOT_COMCONSOLE_SPEED?=9600
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CFLAGS+= -DCONSPEED=${BOOT_COMCONSOLE_SPEED}
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# Enable code to take the default boot string from a fixed location on the
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# disk. See nextboot(8) and README.386BSD for more info.
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@ -24,7 +24,7 @@
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* the rights to redistribute these changes.
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*
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* from: Mach, Revision 2.2 92/04/04 11:34:26 rpd
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* $Id: serial.S,v 1.6 1997/07/14 12:34:01 kato Exp $
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* $Id: serial.S,v 1.7 1998/01/02 09:29:15 kato Exp $
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*/
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/*
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@ -65,17 +65,16 @@ WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*/
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#if COMCONSOLE == 0x238
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#include "../../../i386/boot/biosboot/serial.S"
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#else
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/*
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* modified for PC-98 by KATO T. of Nagoya University
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*/
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.file "serial.S"
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#ifdef PC98
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#include <pc98/pc98/sioreg.h>
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#else
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#include <i386/isa/sioreg.h>
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#endif
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#include "asm.h"
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.text
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@ -199,3 +198,4 @@ ENTRY(init_serial)
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outb %al, %dx
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ret
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#endif
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1311
sys/pc98/cbus/sio.c
1311
sys/pc98/cbus/sio.c
File diff suppressed because it is too large
Load Diff
1311
sys/pc98/pc98/sio.c
1311
sys/pc98/pc98/sio.c
File diff suppressed because it is too large
Load Diff
@ -1,119 +0,0 @@
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)comreg.h 7.2 (Berkeley) 5/9/91
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* $Id: sioreg.h,v 1.6 1997/06/04 10:27:53 kato Exp $
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*/
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/* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */
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#if defined(PC98)
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#define COMBRD(x) (7372800 / (16*(x)))
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#else
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#define COMBRD(x) (1843200 / (16*(x)))
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#endif
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/* interrupt enable register */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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/* interrupt identification register */
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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#define IIR_RXRDY 0x4
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#define IIR_TXRDY 0x2
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#define IIR_NOPEND 0x1
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_RX_LOW 0x00
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#define FIFO_RX_MEDL 0x40
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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/* character format control register */
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#define CFCR_DLAB 0x80
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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#define CFCR_PONE 0x20
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#define CFCR_PEVEN 0x10
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#define CFCR_PODD 0x00
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#define CFCR_PENAB 0x08
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#define CFCR_STOPB 0x04
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#define CFCR_8BITS 0x03
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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/* modem control register */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* line status register */
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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/* modem status register */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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/* speed to initialize to during chip tests */
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#define SIO_TEST_SPEED 9600
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/* default serial console speed if not set with sysctl or probed from boot */
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#ifndef CONSPEED
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#define CONSPEED 9600
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#endif
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