Use correct length mask for split transactions. The hardware would
sometimes put non-zero values in the upper length bits, which are available for high-speed-only USB transactions, breaking the reception of data.
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@ -510,7 +510,10 @@ saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *t
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td->error_any = 1;
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goto complete;
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}
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count = (status & SOTG_PTD_DW3_XFER_COUNT);
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if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
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count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
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else
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count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
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got_short = 0;
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/* verify the packet byte count */
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@ -700,7 +703,10 @@ saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *t
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td->error_any = 1;
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goto complete;
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}
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count = (status & SOTG_PTD_DW3_XFER_COUNT);
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if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
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count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
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else
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count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
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got_short = 0;
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/* verify the packet byte count */
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@ -895,7 +901,10 @@ saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *t
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} else if (status & SOTG_PTD_DW3_HALTED) {
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goto complete;
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}
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count = (status & SOTG_PTD_DW3_XFER_COUNT);
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if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
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count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
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else
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count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
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/* verify the packet byte count */
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if (count != td->max_packet_size) {
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@ -211,7 +211,8 @@
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#define SOTG_PTD_DW3_CERR_3 (3U << 23)
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#define SOTG_PTD_DW3_CERR_2 (2U << 23) /* infinite NAKs */
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#define SOTG_PTD_DW3_CERR_1 (1U << 23)
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#define SOTG_PTD_DW3_XFER_COUNT 0x7FFF
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#define SOTG_PTD_DW3_XFER_COUNT_HS 0x7FFF
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#define SOTG_PTD_DW3_XFER_COUNT_SPLIT 0x03FF
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#define SOTG_PTD_DW4 16
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#define SOTG_PTD_DW5 20
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#define SOTG_PTD_DW6 24
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