diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h index 415e150ba354..436a980785c4 100644 --- a/sys/mips/include/cpuregs.h +++ b/sys/mips/include/cpuregs.h @@ -521,7 +521,6 @@ #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ #define MIPS_CONFIG1_TLBSZ_SHIFT 25 -#define MIPS_MAX_TLB_ENTRIES 128 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ #define MIPS_CONFIG1_IS_SHIFT 22 diff --git a/sys/mips/mips/tlb.c b/sys/mips/mips/tlb.c index 2c1fcb550be9..9907ce96801a 100644 --- a/sys/mips/mips/tlb.c +++ b/sys/mips/mips/tlb.c @@ -40,6 +40,14 @@ #include #include +#if defined(CPU_CNMIPS) +#define MIPS_MAX_TLB_ENTRIES 128 +#elif defined(CPU_NLM) +#define MIPS_MAX_TLB_ENTRIES (2048 + 128) +#else +#define MIPS_MAX_TLB_ENTRIES 64 +#endif + struct tlb_state { unsigned wired; struct tlb_entry { @@ -264,12 +272,15 @@ tlb_invalidate_range(pmap_t pmap, vm_offset_t start, vm_offset_t end) void tlb_save(void) { - unsigned i, cpu; + unsigned ntlb, i, cpu; cpu = PCPU_GET(cpuid); - + if (num_tlbentries > MIPS_MAX_TLB_ENTRIES) + ntlb = MIPS_MAX_TLB_ENTRIES; + else + ntlb = num_tlbentries; tlb_state[cpu].wired = mips_rd_wired(); - for (i = 0; i < num_tlbentries; i++) { + for (i = 0; i < ntlb; i++) { mips_wr_index(i); tlb_read(); @@ -329,7 +340,7 @@ tlb_invalidate_one(unsigned i) DB_SHOW_COMMAND(tlb, ddb_dump_tlb) { register_t ehi, elo0, elo1; - unsigned i, cpu; + unsigned i, cpu, ntlb; /* * XXX @@ -344,12 +355,18 @@ DB_SHOW_COMMAND(tlb, ddb_dump_tlb) db_printf("Invalid CPU %u\n", cpu); return; } + if (num_tlbentries > MIPS_MAX_TLB_ENTRIES) { + ntlb = MIPS_MAX_TLB_ENTRIES; + db_printf("Warning: Only %d of %d TLB entries saved!\n", + ntlb, num_tlbentries); + } else + ntlb = num_tlbentries; if (cpu == PCPU_GET(cpuid)) tlb_save(); db_printf("Beginning TLB dump for CPU %u...\n", cpu); - for (i = 0; i < num_tlbentries; i++) { + for (i = 0; i < ntlb; i++) { if (i == tlb_state[cpu].wired) { if (i != 0) db_printf("^^^ WIRED ENTRIES ^^^\n");