riscv pmap: zero reserved pte bits in ppn
The top 10 bits of a pte are reserved by specification[1] and are not part of the PPN. [1] 'Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified', '4.4.1 Addressing and Memory Protection', page 72: "The PTE format for Sv39 is shown in Figure 4.18. ... Bits 63–54 are reserved for future use and must be zeroed by software for forward compatibility." Submitted by: Nathaniel Filardo <nwf20@cl.cam.ac.uk> Reviewed by: kp, mhorne Differential Revision: https://reviews.freebsd.org/D25523
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@ -83,6 +83,9 @@ typedef uint64_t pn_t; /* page number */
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#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \
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PTE_SW_MANAGED | PTE_SW_WIRED)
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/* Bits 63 - 54 are reserved for future use. */
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#define PTE_HI_MASK 0xFFC0000000000000ULL
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#define PTE_PPN0_S 10
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#define PTE_PPN1_S 19
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#define PTE_PPN2_S 28
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@ -339,7 +339,8 @@ pagezero(void *p)
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#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
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#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
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#define PTE_TO_PHYS(pte) ((pte >> PTE_PPN0_S) * PAGE_SIZE)
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#define PTE_TO_PHYS(pte) \
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((((pte) & ~PTE_HI_MASK) >> PTE_PPN0_S) * PAGE_SIZE)
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static __inline pd_entry_t *
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pmap_l1(pmap_t pmap, vm_offset_t va)
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