Add locking to mlx(4) to make it MPSAFE along with some other fixes:
- Use callout(9) rather than timeout(9). - Add a mutex as an I/O lock that protects the adapter and is used for the I/O path. - Add an sx lock as a configuration lock that protects the relationship of configured volumes. - Freeze the request queue when a DMA load is deferred with EINPROGRESS and unfreeze the queue when the DMA callback is invoked. - Explicitly poll the hardware while waiting to submit a command to allow completed commands to free up slots in the command ring. - Remove driver-wide 'initted' variable from mlx_*_fw_handshake() routines. That state should be per-controller instead. Add it as an argument since the first caller knows when it is the first caller. - Remove explicit bus_space tag/handle and use bus_*() rather than bus_space_*(). - Move duplicated PCI device ID probing into a mlx_pci_match() routine. - Don't check for PCIM_CMD_MEMEN (the PCI bus will enable that when allocating the resource) and use pci_enable_busmaster() rather than manipulating the register directly. Tested by: no one despite multiple requests (hope it works)
This commit is contained in:
John Baldwin
parent
8b3daf895a
commit
0fca6f8bf5
File diff suppressed because it is too large
Load Diff
@ -36,7 +36,9 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/sx.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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@ -84,10 +86,17 @@ mlxd_open(struct disk *dp)
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return (ENXIO);
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/* controller not active? */
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if (sc->mlxd_controller->mlx_state & MLX_STATE_SHUTDOWN)
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MLX_CONFIG_LOCK(sc->mlxd_controller);
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MLX_IO_LOCK(sc->mlxd_controller);
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if (sc->mlxd_controller->mlx_state & MLX_STATE_SHUTDOWN) {
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MLX_IO_UNLOCK(sc->mlxd_controller);
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MLX_CONFIG_UNLOCK(sc->mlxd_controller);
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return(ENXIO);
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}
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sc->mlxd_flags |= MLXD_OPEN;
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MLX_IO_UNLOCK(sc->mlxd_controller);
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MLX_CONFIG_UNLOCK(sc->mlxd_controller);
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return (0);
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}
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@ -97,10 +106,14 @@ mlxd_close(struct disk *dp)
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struct mlxd_softc *sc = (struct mlxd_softc *)dp->d_drv1;
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debug_called(1);
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if (sc == NULL)
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return (ENXIO);
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MLX_CONFIG_LOCK(sc->mlxd_controller);
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MLX_IO_LOCK(sc->mlxd_controller);
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sc->mlxd_flags &= ~MLXD_OPEN;
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MLX_IO_UNLOCK(sc->mlxd_controller);
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MLX_CONFIG_UNLOCK(sc->mlxd_controller);
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return (0);
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}
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@ -142,13 +155,16 @@ mlxd_strategy(mlx_bio *bp)
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}
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/* XXX may only be temporarily offline - sleep? */
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MLX_IO_LOCK(sc->mlxd_controller);
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if (sc->mlxd_drive->ms_state == MLX_SYSD_OFFLINE) {
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MLX_IO_UNLOCK(sc->mlxd_controller);
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MLX_BIO_SET_ERROR(bp, ENXIO);
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goto bad;
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}
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MLX_BIO_STATS_START(bp);
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mlx_submit_buf(sc->mlxd_controller, bp);
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MLX_IO_UNLOCK(sc->mlxd_controller);
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return;
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bad:
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@ -232,7 +248,6 @@ mlxd_attach(device_t dev)
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sc->mlxd_disk->d_mediasize = MLX_BLKSIZE * (off_t)sc->mlxd_drive->ms_size;
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sc->mlxd_disk->d_fwsectors = sc->mlxd_drive->ms_sectors;
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sc->mlxd_disk->d_fwheads = sc->mlxd_drive->ms_heads;
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sc->mlxd_disk->d_flags = DISKFLAG_NEEDSGIANT;
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/*
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* Set maximum I/O size to the lesser of the recommended maximum and the practical
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@ -30,7 +30,10 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/sx.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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@ -88,6 +91,21 @@ struct mlx_ident
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{0, 0, 0, 0, 0, 0}
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};
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static struct mlx_ident *
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mlx_pci_match(device_t dev)
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{
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struct mlx_ident *m;
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for (m = mlx_identifiers; m->vendor != 0; m++) {
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if ((m->vendor == pci_get_vendor(dev)) &&
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(m->device == pci_get_device(dev)) &&
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((m->subvendor == 0) || ((m->subvendor == pci_get_subvendor(dev)) &&
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(m->subdevice == pci_get_subdevice(dev)))))
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return (m);
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}
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return (NULL);
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}
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static int
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mlx_pci_probe(device_t dev)
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{
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@ -95,15 +113,10 @@ mlx_pci_probe(device_t dev)
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debug_called(1);
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for (m = mlx_identifiers; m->vendor != 0; m++) {
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if ((m->vendor == pci_get_vendor(dev)) &&
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(m->device == pci_get_device(dev)) &&
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((m->subvendor == 0) || ((m->subvendor == pci_get_subvendor(dev)) &&
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(m->subdevice == pci_get_subdevice(dev))))) {
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device_set_desc(dev, m->desc);
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return(BUS_PROBE_DEFAULT);
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}
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m = mlx_pci_match(dev);
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if (m != NULL) {
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device_set_desc(dev, m->desc);
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return(BUS_PROBE_DEFAULT);
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}
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return(ENXIO);
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}
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@ -112,45 +125,29 @@ static int
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mlx_pci_attach(device_t dev)
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{
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struct mlx_softc *sc;
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int i, error;
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u_int32_t command;
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struct mlx_ident *m;
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int error;
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debug_called(1);
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/*
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* Make sure we are going to be able to talk to this board.
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*/
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command = pci_read_config(dev, PCIR_COMMAND, 2);
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if ((command & PCIM_CMD_MEMEN) == 0) {
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device_printf(dev, "memory window not available\n");
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return(ENXIO);
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}
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/* force the busmaster enable bit on */
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command |= PCIM_CMD_BUSMASTEREN;
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pci_write_config(dev, PCIR_COMMAND, command, 2);
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pci_enable_busmaster(dev);
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/*
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* Initialise softc.
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*/
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sc = device_get_softc(dev);
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bzero(sc, sizeof(*sc));
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sc->mlx_dev = dev;
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/*
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* Work out what sort of adapter this is (we need to know this in order
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* to map the appropriate interface resources).
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*/
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sc->mlx_iftype = 0;
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for (i = 0; mlx_identifiers[i].vendor != 0; i++) {
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if ((mlx_identifiers[i].vendor == pci_get_vendor(dev)) &&
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(mlx_identifiers[i].device == pci_get_device(dev))) {
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sc->mlx_iftype = mlx_identifiers[i].iftype;
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break;
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}
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}
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if (sc->mlx_iftype == 0) /* shouldn't happen */
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m = mlx_pci_match(dev);
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if (m == NULL) /* shouldn't happen */
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return(ENXIO);
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sc->mlx_iftype = m->iftype;
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mtx_init(&sc->mlx_io_lock, "mlx I/O", NULL, MTX_DEF);
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sx_init(&sc->mlx_config_lock, "mlx config");
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callout_init_mtx(&sc->mlx_timeout, &sc->mlx_io_lock, 0);
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/*
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* Allocate the PCI register window.
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*/
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@ -183,8 +180,6 @@ mlx_pci_attach(device_t dev)
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mlx_free(sc);
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return(ENXIO);
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}
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sc->mlx_btag = rman_get_bustag(sc->mlx_mem);
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sc->mlx_bhandle = rman_get_bushandle(sc->mlx_mem);
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/*
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* Allocate the parent bus DMA tag appropriate for PCI.
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@ -78,18 +78,18 @@
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#define MLX_V3_FWERROR_PARAM1 0x00
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#define MLX_V3_FWERROR_PARAM2 0x01
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#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_MAILBOX + idx, val)
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#define MLX_V3_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS_IDENT)
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#define MLX_V3_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS)
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#define MLX_V3_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR)
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#define MLX_V3_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR, val)
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#define MLX_V3_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR)
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#define MLX_V3_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR, val)
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#define MLX_V3_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IER, val)
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#define MLX_V3_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR)
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#define MLX_V3_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR, val)
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#define MLX_V3_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR_PARAM1)
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#define MLX_V3_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR_PARAM2)
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#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V3_MAILBOX + idx, val)
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#define MLX_V3_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V3_STATUS_IDENT)
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#define MLX_V3_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V3_STATUS)
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#define MLX_V3_GET_IDBR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_IDBR)
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#define MLX_V3_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IDBR, val)
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#define MLX_V3_GET_ODBR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_ODBR)
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#define MLX_V3_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_ODBR, val)
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#define MLX_V3_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IER, val)
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#define MLX_V3_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR)
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#define MLX_V3_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_FWERROR, val)
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#define MLX_V3_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR_PARAM1)
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#define MLX_V3_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR_PARAM2)
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#define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */
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#define MLX_V3_IDB_INIT_BUSY (1<<1) /* initialisation in progress */
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@ -115,18 +115,18 @@
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#define MLX_V4_FWERROR_PARAM2 0x1001
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/* use longword access? */
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#define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_MAILBOX + idx, val)
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#define MLX_V4_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_STATUS_IDENT)
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#define MLX_V4_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_STATUS)
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#define MLX_V4_GET_IDBR(sc) bus_space_read_4 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IDBR)
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#define MLX_V4_PUT_IDBR(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IDBR, val)
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#define MLX_V4_GET_ODBR(sc) bus_space_read_4 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_ODBR)
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#define MLX_V4_PUT_ODBR(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_ODBR, val)
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#define MLX_V4_PUT_IER(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IER, val)
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#define MLX_V4_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR)
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#define MLX_V4_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR, val)
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#define MLX_V4_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR_PARAM1)
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#define MLX_V4_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR_PARAM2)
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#define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V4_MAILBOX + idx, val)
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#define MLX_V4_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V4_STATUS_IDENT)
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#define MLX_V4_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V4_STATUS)
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#define MLX_V4_GET_IDBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_IDBR)
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#define MLX_V4_PUT_IDBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IDBR, val)
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#define MLX_V4_GET_ODBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_ODBR)
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#define MLX_V4_PUT_ODBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_ODBR, val)
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#define MLX_V4_PUT_IER(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IER, val)
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#define MLX_V4_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR)
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#define MLX_V4_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V4_FWERROR, val)
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#define MLX_V4_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR_PARAM1)
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#define MLX_V4_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR_PARAM2)
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#define MLX_V4_IDB_FULL (1<<0) /* mailbox is full */
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#define MLX_V4_IDB_INIT_BUSY (1<<1) /* initialisation in progress */
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@ -160,18 +160,18 @@
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#define MLX_V5_FWERROR_PARAM1 0x50
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#define MLX_V5_FWERROR_PARAM2 0x51
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#define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_MAILBOX + idx, val)
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#define MLX_V5_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_STATUS_IDENT)
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#define MLX_V5_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_STATUS)
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#define MLX_V5_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IDBR)
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#define MLX_V5_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IDBR, val)
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#define MLX_V5_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_ODBR)
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#define MLX_V5_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_ODBR, val)
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#define MLX_V5_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IER, val)
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#define MLX_V5_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR)
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#define MLX_V5_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR, val)
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#define MLX_V5_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR_PARAM1)
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#define MLX_V5_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR_PARAM2)
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#define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V5_MAILBOX + idx, val)
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#define MLX_V5_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V5_STATUS_IDENT)
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#define MLX_V5_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V5_STATUS)
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#define MLX_V5_GET_IDBR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_IDBR)
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#define MLX_V5_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IDBR, val)
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#define MLX_V5_GET_ODBR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_ODBR)
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#define MLX_V5_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_ODBR, val)
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#define MLX_V5_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IER, val)
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#define MLX_V5_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR)
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#define MLX_V5_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_FWERROR, val)
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#define MLX_V5_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR_PARAM1)
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#define MLX_V5_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR_PARAM2)
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#define MLX_V5_IDB_EMPTY (1<<0) /* mailbox is empty */
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#define MLX_V5_IDB_INIT_DONE (1<<1) /* initialisation has completed */
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@ -113,8 +113,6 @@ struct mlx_softc
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struct resource *mlx_mem; /* mailbox interface window */
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int mlx_mem_rid;
|
||||
int mlx_mem_type;
|
||||
bus_space_handle_t mlx_bhandle; /* bus space handle */
|
||||
bus_space_tag_t mlx_btag; /* bus space tag */
|
||||
bus_dma_tag_t mlx_parent_dmat;/* parent DMA tag */
|
||||
bus_dma_tag_t mlx_buffer_dmat;/* data buffer DMA tag */
|
||||
struct resource *mlx_irq; /* interrupt */
|
||||
@ -149,7 +147,10 @@ struct mlx_softc
|
||||
#define MLX_STATE_SHUTDOWN (1<<1) /* controller is shut down */
|
||||
#define MLX_STATE_OPEN (1<<2) /* control device is open */
|
||||
#define MLX_STATE_SUSPEND (1<<3) /* controller is suspended */
|
||||
struct callout_handle mlx_timeout; /* periodic status monitor */
|
||||
#define MLX_STATE_QFROZEN (1<<4) /* bio queue frozen */
|
||||
struct mtx mlx_io_lock;
|
||||
struct sx mlx_config_lock;
|
||||
struct callout mlx_timeout; /* periodic status monitor */
|
||||
time_t mlx_lastpoll; /* last time_second we polled for status */
|
||||
u_int16_t mlx_lastevent; /* sequence number of the last event we recorded */
|
||||
int mlx_currevent; /* sequence number last time we looked */
|
||||
@ -160,7 +161,6 @@ struct mlx_softc
|
||||
struct mlx_rebuild_status mlx_rebuildstat; /* last rebuild status */
|
||||
struct mlx_pause mlx_pause; /* pending pause operation details */
|
||||
|
||||
int mlx_locks; /* reentrancy avoidance */
|
||||
int mlx_flags;
|
||||
#define MLX_SPINUP_REPORTED (1<<0) /* "spinning up drives" message displayed */
|
||||
#define MLX_EVENTLOG_BUSY (1<<1) /* currently reading event log */
|
||||
@ -174,34 +174,17 @@ struct mlx_softc
|
||||
int (* mlx_tryqueue)(struct mlx_softc *sc, struct mlx_command *mc);
|
||||
int (* mlx_findcomplete)(struct mlx_softc *sc, u_int8_t *slot, u_int16_t *status);
|
||||
void (* mlx_intaction)(struct mlx_softc *sc, int action);
|
||||
int (* mlx_fw_handshake)(struct mlx_softc *sc, int *error, int *param1, int *param2);
|
||||
int (* mlx_fw_handshake)(struct mlx_softc *sc, int *error, int *param1, int *param2, int first);
|
||||
#define MLX_INTACTION_DISABLE 0
|
||||
#define MLX_INTACTION_ENABLE 1
|
||||
};
|
||||
|
||||
/*
|
||||
* Simple (stupid) locks.
|
||||
*
|
||||
* Note that these are designed to avoid reentrancy, not concurrency, and will
|
||||
* need to be replaced with something better.
|
||||
*/
|
||||
#define MLX_LOCK_COMPLETING (1<<0)
|
||||
#define MLX_LOCK_STARTING (1<<1)
|
||||
|
||||
static __inline int
|
||||
mlx_lock_tas(struct mlx_softc *sc, int lock)
|
||||
{
|
||||
if ((sc)->mlx_locks & (lock))
|
||||
return(1);
|
||||
atomic_set_int(&sc->mlx_locks, lock);
|
||||
return(0);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
mlx_lock_clr(struct mlx_softc *sc, int lock)
|
||||
{
|
||||
atomic_clear_int(&sc->mlx_locks, lock);
|
||||
}
|
||||
#define MLX_IO_LOCK(sc) mtx_lock(&(sc)->mlx_io_lock)
|
||||
#define MLX_IO_UNLOCK(sc) mtx_unlock(&(sc)->mlx_io_lock)
|
||||
#define MLX_IO_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mlx_io_lock, MA_OWNED)
|
||||
#define MLX_CONFIG_LOCK(sc) sx_xlock(&(sc)->mlx_config_lock)
|
||||
#define MLX_CONFIG_UNLOCK(sc) sx_xunlock(&(sc)->mlx_config_lock)
|
||||
#define MLX_CONFIG_ASSERT_LOCKED(sc) sx_assert(&(sc)->mlx_config_lock, SA_XLOCKED)
|
||||
|
||||
/*
|
||||
* Interface between bus connections and driver core.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user