arm64: rockchip: rk3399_clk: Add sd clock definitions
MFC after: 1 week
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@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$");
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#define PCLK_I2C5 344
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#define PCLK_I2C6 345
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#define PCLK_I2C7 346
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#define HCLK_SDMMC 462
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static struct rk_cru_gate rk3399_gates[] = {
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/* CRU_CLKGATE_CON0 */
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@ -99,6 +100,9 @@ static struct rk_cru_gate rk3399_gates[] = {
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CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
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CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
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CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
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/* CRU_CLKGATE_CON33 */
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CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
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};
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@ -1385,6 +1389,60 @@ static struct rk_clk_armclk_def armclk_b = {
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.nrates = nitems(rk3399_armclkb_rates),
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};
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/*
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* sdmmc
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*/
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#define HCLK_SD 461
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static const char *hclk_sd_parents[] = {"cpll", "gpll"};
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static struct rk_clk_composite_def hclk_sd = {
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.clkdef = {
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.id = HCLK_SD,
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.name = "hclk_sd",
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.parent_names = hclk_sd_parents,
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.parent_cnt = nitems(hclk_sd_parents),
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},
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.muxdiv_offset = 0x134,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 8,
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.div_width = 5,
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.gate_offset = 0x330,
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.gate_shift = 13,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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#define SCLK_SDMMC 76
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static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};
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static struct rk_clk_composite_def sclk_sdmmc = {
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.clkdef = {
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.id = SCLK_SDMMC,
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.name = "sclk_sdmmc",
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.parent_names = sclk_sdmmc_parents,
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.parent_cnt = nitems(sclk_sdmmc_parents),
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},
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.muxdiv_offset = 0x140,
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.mux_shift = 8,
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.mux_width = 3,
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.div_shift = 0,
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.div_width = 7,
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.gate_offset = 0x318,
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.gate_shift = 1,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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static struct rk_clk rk3399_clks[] = {
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{
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.type = RK3399_CLK_PLL,
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@ -1484,6 +1542,15 @@ static struct rk_clk rk3399_clks[] = {
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.type = RK_CLK_ARMCLK,
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.clk.armclk = &armclk_b,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &hclk_sd,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &sclk_sdmmc,
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},
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};
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static int
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