diff --git a/tools/tools/ath/Makefile b/tools/tools/ath/Makefile index 34c732a59399..16a87aedaef6 100644 --- a/tools/tools/ath/Makefile +++ b/tools/tools/ath/Makefile @@ -1,5 +1,5 @@ # $FreeBSD$ -SUBDIR= athstats athdebug +SUBDIR= athdebug athkey athprom athregs athstats .include diff --git a/tools/tools/ath/Makefile.inc b/tools/tools/ath/Makefile.inc new file mode 100644 index 000000000000..68ea6a9885cc --- /dev/null +++ b/tools/tools/ath/Makefile.inc @@ -0,0 +1,11 @@ +# $FreeBSD$ + +BINDIR= /usr/local/bin +NO_MAN= + +ATH_DEFAULT= ath0 + +CFLAGS+=-DATH_DEFAULT='"${ATH_DEFAULT}"' +CFLAGS+=-I../common +CFLAGS+=-I../../../../sys/dev/ath +CFLAGS+=-I../../../../sys/dev/ath/ath_hal diff --git a/tools/tools/ath/athdebug/Makefile b/tools/tools/ath/athdebug/Makefile index c1b3bf981678..0b75f26662b0 100644 --- a/tools/tools/ath/athdebug/Makefile +++ b/tools/tools/ath/athdebug/Makefile @@ -1,7 +1,7 @@ # $FreeBSD$ PROG= athdebug -BINDIR= /usr/local/bin -NO_MAN= + +.include <../Makefile.inc> .include diff --git a/tools/tools/ath/athkey/Makefile b/tools/tools/ath/athkey/Makefile new file mode 100644 index 000000000000..7398a4106475 --- /dev/null +++ b/tools/tools/ath/athkey/Makefile @@ -0,0 +1,7 @@ +# $FreeBSD$ + +PROG= athkey + +.include <../Makefile.inc> + +.include diff --git a/tools/tools/ath/athkey/athkey.c b/tools/tools/ath/athkey/athkey.c new file mode 100644 index 000000000000..d25410554d72 --- /dev/null +++ b/tools/tools/ath/athkey/athkey.c @@ -0,0 +1,203 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" + +#include +#include +#include +#include +#include + +const char *progname; + +static int +toint(int c) +{ + return isdigit(c) ? c - '0' : isupper(c) ? c - 'A' + 10 : c - 'a' + 10; +} + +static int +getdata(const char *arg, u_int8_t *data, size_t maxlen) +{ + const char *cp = arg; + int len; + + if (cp[0] == '0' && (cp[1] == 'x' || cp[1] == 'X')) + cp += 2; + len = 0; + while (*cp) { + int b0, b1; + if (cp[0] == ':' || cp[0] == '-' || cp[0] == '.') { + cp++; + continue; + } + if (!isxdigit(cp[0])) { + fprintf(stderr, "%s: invalid data value %c (not hex)\n", + progname, cp[0]); + exit(-1); + } + b0 = toint(cp[0]); + if (cp[1] != '\0') { + if (!isxdigit(cp[1])) { + fprintf(stderr, "%s: invalid data value %c " + "(not hex)\n", progname, cp[1]); + exit(-1); + } + b1 = toint(cp[1]); + cp += 2; + } else { /* fake up 0 */ + b1 = b0, b0 = 0; + cp += 1; + } + if (len > maxlen) { + fprintf(stderr, + "%s: too much data in %s, max %u bytes\n", + progname, arg, maxlen); + } + data[len++] = (b0<<4) | b1; + } + return len; +} + +/* XXX this assumes 5212 key types are common to 5211 and 5210 */ + +static int +getcipher(const char *name) +{ +#define streq(a,b) (strcasecmp(a,b) == 0) + + if (streq(name, "wep")) + return HAL_CIPHER_WEP; + if (streq(name, "tkip")) + return HAL_CIPHER_TKIP; + if (streq(name, "aes-ocb") || streq(name, "ocb")) + return HAL_CIPHER_AES_OCB; + if (streq(name, "aes-ccm") || streq(name, "ccm") || + streq(name, "aes")) + return HAL_CIPHER_AES_CCM; + if (streq(name, "ckip")) + return HAL_CIPHER_CKIP; + if (streq(name, "none") || streq(name, "clr")) + return HAL_CIPHER_CLR; + + fprintf(stderr, "%s: unknown cipher %s\n", progname, name); + exit(-1); +#undef streq +} + +static void +usage(void) +{ + fprintf(stderr, "usage: %s [-i device] keyix cipher keyval [mac]\n", + progname); + exit(-1); +} + +int +main(int argc, char *argv[]) +{ + const char *ifname; + struct ath_diag atd; + HAL_DIAG_KEYVAL setkey; + const char *cp; + int s, c; + u_int16_t keyix; + int op = HAL_DIAG_SETKEY; + int xor = 0; + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) + err(1, "socket"); + ifname = getenv("ATH"); + if (!ifname) + ifname = ATH_DEFAULT; + + progname = argv[0]; + while ((c = getopt(argc, argv, "di:x")) != -1) + switch (c) { + case 'd': + op = HAL_DIAG_RESETKEY; + break; + case 'i': + ifname = optarg; + break; + case 'x': + xor = 1; + break; + default: + usage(); + /*NOTREACHED*/ + } + argc -= optind; + argv += optind; + if (argc < 1) + usage(); + + keyix = (u_int16_t) atoi(argv[0]); + if (keyix > 127) + errx(-1, "%s: invalid key index %s, must be [0..127]", + progname, argv[0]); + strncpy(atd.ad_name, ifname, sizeof (atd.ad_name)); + atd.ad_id = op | ATH_DIAG_IN | ATH_DIAG_DYN; + atd.ad_out_data = NULL; + atd.ad_out_size = 0; + switch (op) { + case HAL_DIAG_RESETKEY: + atd.ad_in_data = (caddr_t) &keyix; + atd.ad_in_size = sizeof(u_int16_t); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + return 0; + case HAL_DIAG_SETKEY: + if (argc != 3 && argc != 4) + usage(); + memset(&setkey, 0, sizeof(setkey)); + setkey.dk_keyix = keyix; + setkey.dk_xor = xor; + setkey.dk_keyval.kv_type = getcipher(argv[1]); + setkey.dk_keyval.kv_len = getdata(argv[2], + setkey.dk_keyval.kv_val, sizeof(setkey.dk_keyval.kv_val)); + /* XXX MIC */ + if (argc == 4) + (void) getdata(argv[3], setkey.dk_mac, + IEEE80211_ADDR_LEN); + atd.ad_in_data = (caddr_t) &setkey; + atd.ad_in_size = sizeof(setkey); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + return 0; + } + return -1; +} diff --git a/tools/tools/ath/athpow/Makefile b/tools/tools/ath/athpow/Makefile new file mode 100644 index 000000000000..f3b36731db16 --- /dev/null +++ b/tools/tools/ath/athpow/Makefile @@ -0,0 +1,7 @@ +# $FreeBSD$ + +PROG= athpow + +.include <../Makefile.inc> + +.include diff --git a/tools/tools/ath/athpow/athpow.c b/tools/tools/ath/athpow/athpow.c new file mode 100644 index 000000000000..a798e7fd5233 --- /dev/null +++ b/tools/tools/ath/athpow/athpow.c @@ -0,0 +1,198 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include +#include +#include + +#include "ah.h" +#include "ah_internal.h" +#include "ah_eeprom.h" +#include "ah_eeprom_v1.h" +#include "ah_eeprom_v3.h" +#include "ah_eeprom_v14.h" +#include "ar5212/ar5212reg.h" +#define IS_5112(ah) \ + (((ah)->ah_analog5GhzRev&0xf0) >= AR_RAD5112_SREV_MAJOR \ + && ((ah)->ah_analog5GhzRev&0xf0) < AR_RAD2316_SREV_MAJOR ) +#define IS_2316(ah) \ + ((ah)->ah_macVersion == AR_SREV_2415) +#define IS_2413(ah) \ + ((ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) +#define IS_5424(ah) \ + ((ah)->ah_macVersion == AR_SREV_5424 || \ + ((ah)->ah_macVersion == AR_SREV_5413 && \ + (ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) +#define IS_5413(ah) \ + ((ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) + +#ifndef MAX +#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +static void printPcdacTable(FILE *fd, u_int16_t pcdac[], u_int n); +static void printPowerPerRate(FILE *fd, u_int16_t ratesArray[], u_int n); +static void printRevs(FILE *fd, const HAL_REVS *revs); + +static void +usage(const char *progname) +{ + fprintf(stderr, "usage: %s [-v] [-i dev]\n", progname); + exit(1); +} + +int +main(int argc, char *argv[]) +{ + int s, i, verbose = 0, c; + struct ath_diag atd; + const char *ifname; + HAL_REVS revs; + u_int16_t pcdacTable[MAX(PWR_TABLE_SIZE,PWR_TABLE_SIZE_2413)]; + u_int16_t ratesArray[16]; + u_int nrates, npcdac; + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) + err(1, "socket"); + ifname = getenv("ATH"); + if (!ifname) + ifname = ATH_DEFAULT; + while ((c = getopt(argc, argv, "i:v")) != -1) + switch (c) { + case 'i': + ifname = optarg; + break; + case 'v': + verbose++; + break; + default: + usage(argv[0]); + } + strncpy(atd.ad_name, ifname, sizeof (atd.ad_name)); + + atd.ad_id = HAL_DIAG_REVS; + atd.ad_out_data = (caddr_t) &revs; + atd.ad_out_size = sizeof(revs); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + + if (verbose) + printRevs(stdout, &revs); + + atd.ad_id = HAL_DIAG_TXRATES; + atd.ad_out_data = (caddr_t) ratesArray; + atd.ad_out_size = sizeof(ratesArray); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + nrates = sizeof(ratesArray) / sizeof(u_int16_t); + + atd.ad_id = HAL_DIAG_PCDAC; + atd.ad_out_data = (caddr_t) pcdacTable; + atd.ad_out_size = sizeof(pcdacTable); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + if (IS_2413(&revs) || IS_5413(&revs)) + npcdac = PWR_TABLE_SIZE_2413; + else + npcdac = PWR_TABLE_SIZE; + + printf("PCDAC table:\n"); + printPcdacTable(stdout, pcdacTable, npcdac); + + printf("Power per rate table:\n"); + printPowerPerRate(stdout, ratesArray, nrates); + + return 0; +} + +static void +printPcdacTable(FILE *fd, u_int16_t pcdac[], u_int n) +{ + int i, halfRates = n/2; + + for (i = 0; i < halfRates; i += 2) + fprintf(fd, "[%2u] %04x %04x [%2u] %04x %04x\n", + i, pcdac[2*i + 1], pcdac[2*i], + i+1, pcdac[2*(i+1) + 1], pcdac[2*(i+1)]); +} + +static void +printPowerPerRate(FILE *fd, u_int16_t ratesArray[], u_int n) +{ + const char *rateString[] = { + " 6mb OFDM", " 9mb OFDM", "12mb OFDM", "18mb OFDM", + "24mb OFDM", "36mb OFDM", "48mb OFDM", "54mb OFDM", + "1L CCK ", "2L CCK ", "2S CCK ", "5.5L CCK ", + "5.5S CCK ", "11L CCK ", "11S CCK ", "XR " + }; + int i, halfRates = n/2; + + for (i = 0; i < halfRates; i++) + fprintf(fd, " %s %3d.%1d dBm | %s %3d.%1d dBm\n", + rateString[i], ratesArray[i]/2, + (ratesArray[i] %2) * 5, + rateString[i + halfRates], + ratesArray[i + halfRates]/2, + (ratesArray[i + halfRates] %2) *5); +} + +static void +printRevs(FILE *fd, const HAL_REVS *revs) +{ + const char *rfbackend; + + fprintf(fd, "PCI device id 0x%x subvendor id 0x%x\n", + revs->ah_devid, revs->ah_subvendorid); + fprintf(fd, "mac %d.%d phy %d.%d" + , revs->ah_macVersion, revs->ah_macRev + , revs->ah_phyRev >> 4, revs->ah_phyRev & 0xf + ); + rfbackend = IS_5413(revs) ? "5413" : + IS_2413(revs) ? "2413" : + IS_5112(revs) ? "5112" : + "5111"; + if (revs->ah_analog5GhzRev && revs->ah_analog2GhzRev) + fprintf(fd, " 5ghz radio %d.%d 2ghz radio %d.%d (%s)\n" + , revs->ah_analog5GhzRev >> 4 + , revs->ah_analog5GhzRev & 0xf + , revs->ah_analog2GhzRev >> 4 + , revs->ah_analog2GhzRev & 0xf + , rfbackend + ); + else + fprintf(fd, " radio %d.%d (%s)\n" + , revs->ah_analog5GhzRev >> 4 + , revs->ah_analog5GhzRev & 0xf + , rfbackend + ); +} diff --git a/tools/tools/ath/athprom/Makefile b/tools/tools/ath/athprom/Makefile new file mode 100644 index 000000000000..1278f22721ef --- /dev/null +++ b/tools/tools/ath/athprom/Makefile @@ -0,0 +1,17 @@ +# $FreeBSD$ + +PROG= athprom + +.include <../Makefile.inc> + +TEMPLATEDIR= /usr/local/libdata/athprom +TEXTMODE?= 444 + +CFLAGS+=-DDIR_TEMPLATE='"${TEMPLATEDIR}"' + +beforeinstall: + mkdir -p ${DESTDIR}${TEMPLATEDIR} + ${INSTALL} -o ${BINOWN} -g ${BINGRP} -m ${TEXTMODE} \ + ${.CURDIR}/eeprom-* ${DESTDIR}${TEMPLATEDIR}/ + +.include diff --git a/tools/tools/ath/athprom/athprom.c b/tools/tools/ath/athprom/athprom.c new file mode 100644 index 000000000000..bbcf7ac786f2 --- /dev/null +++ b/tools/tools/ath/athprom/athprom.c @@ -0,0 +1,978 @@ +/*- + * Copyright (c) 2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ah_eeprom_v1.h" +#include "ah_eeprom_v3.h" +#include "ah_eeprom_v14.h" + +#define IS_VERS(op, v) (eeprom.ee_version op (v)) + +#include +#include +#include +#include +#include + +#ifndef DIR_TEMPLATE +#define DIR_TEMPLATE "/usr/local/libdata/athprom" +#endif + +struct ath_diag atd; +int s; +const char *progname; +union { + HAL_EEPROM legacy; /* format v3.x ... v5.x */ + struct ar5416eeprom v14; /* 11n format v14.x ... */ +} eep; +#define eeprom eep.legacy +#define eepromN eep.v14 + +static void parseTemplate(FILE *ftemplate, FILE *fd); +static uint16_t eeread(uint16_t); +static void eewrite(uint16_t, uint16_t); + +static void +usage() +{ + fprintf(stderr, "usage: %s [-i ifname] [-t pathname] [offset | offset=value]\n", progname); + exit(-1); +} + +static FILE * +opentemplate(const char *dir) +{ + char filename[PATH_MAX]; + FILE *fd; + + /* find the template using the eeprom version */ + snprintf(filename, sizeof(filename), "%s/eeprom-%d.%d", + dir, eeprom.ee_version >> 12, eeprom.ee_version & 0xfff); + fd = fopen(filename, "r"); + if (fd == NULL && errno == ENOENT) { + /* retry with just the major version */ + snprintf(filename, sizeof(filename), "%s/eeprom-%d", + dir, eeprom.ee_version >> 12); + fd = fopen(filename, "r"); + if (fd != NULL) /* XXX verbose */ + warnx("Using template file %s", filename); + } + return fd; +} + +int +main(int argc, char *argv[]) +{ + FILE *fd = NULL; + const char *ifname; + int c; + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) + err(1, "socket"); + ifname = getenv("ATH"); + if (!ifname) + ifname = ATH_DEFAULT; + + progname = argv[0]; + while ((c = getopt(argc, argv, "i:t:")) != -1) + switch (c) { + case 'i': + ifname = optarg; + break; + case 't': + fd = fopen(optarg, "r"); + if (fd == NULL) + err(-1, "Cannot open %s", optarg); + break; + default: + usage(); + /*NOTREACHED*/ + } + argc -= optind; + argv += optind; + + strncpy(atd.ad_name, ifname, sizeof (atd.ad_name)); + + if (argc != 0) { + for (; argc > 0; argc--, argv++) { + uint16_t off, val, oval; + char line[256]; + char *cp; + + cp = strchr(argv[0], '='); + if (cp != NULL) + *cp = '\0'; + off = (uint16_t) strtoul(argv[0], NULL, 0); + if (off == 0 && errno == EINVAL) + errx(1, "%s: invalid eeprom offset %s", + progname, argv[0]); + if (cp == NULL) { + printf("%04x: %04x\n", off, eeread(off)); + } else { + val = (uint16_t) strtoul(cp+1, NULL, 0); + if (val == 0 && errno == EINVAL) + errx(1, "%s: invalid eeprom value %s", + progname, cp+1); + oval = eeread(off); + printf("Write %04x: %04x = %04x? ", + off, oval, val); + fflush(stdout); + if (fgets(line, sizeof(line), stdin) != NULL && + line[0] == 'y') + eewrite(off, val); + } + } + } else { + atd.ad_id = HAL_DIAG_EEPROM; + atd.ad_out_data = (caddr_t) &eep; + atd.ad_out_size = sizeof(eep); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + if (fd == NULL) { + fd = opentemplate(DIR_TEMPLATE); + if (fd == NULL) + fd = opentemplate("."); + if (fd == NULL) + errx(-1, "Cannot locate template file for " + "v%d.%d EEPROM", eeprom.ee_version >> 12, + eeprom.ee_version & 0xfff); + } + parseTemplate(fd, stdout); + fclose(fd); + } + return 0; +} + +static u_int16_t +eeread(u_int16_t off) +{ + u_int16_t eedata; + + atd.ad_id = HAL_DIAG_EEREAD | ATH_DIAG_IN | ATH_DIAG_DYN; + atd.ad_in_size = sizeof(off); + atd.ad_in_data = (caddr_t) &off; + atd.ad_out_size = sizeof(eedata); + atd.ad_out_data = (caddr_t) &eedata; + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + return eedata; +} + +static void +eewrite(uint16_t off, uint16_t value) +{ + HAL_DIAG_EEVAL eeval; + + eeval.ee_off = off; + eeval.ee_data = value; + + atd.ad_id = HAL_DIAG_EEWRITE | ATH_DIAG_IN; + atd.ad_in_size = sizeof(eeval); + atd.ad_in_data = (caddr_t) &eeval; + atd.ad_out_size = 0; + atd.ad_out_data = NULL; + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); +} + +#define MAXID 128 +int lineno; +int bol; +int curmode = -1; +int curchan; +int curpdgain; /* raw pdgain index */ +int curlpdgain; /* logical pdgain index */ +int curpcdac; +int curctl; +int numChannels; +const RAW_DATA_STRUCT_2413 *pRaw; +const TRGT_POWER_INFO *pPowerInfo; +const DATA_PER_CHANNEL *pDataPerChannel; +const EEPROM_POWER_EXPN_5112 *pExpnPower; +int singleXpd; + +static int +token(FILE *fd, char id[], int maxid, const char *what) +{ + int c, i; + + i = 0; + for (;;) { + c = getc(fd); + if (c == EOF) + return EOF; + if (!isalnum(c) && c != '_') { + ungetc(c, fd); + break; + } + if (i == maxid-1) { + warnx("line %d, %s too long", lineno, what); + break; + } + id[i++] = c; + } + id[i] = '\0'; + if (i != 0) + bol = 0; + return i; +} + +static int +skipto(FILE *fd, const char *what) +{ + char id[MAXID]; + int c; + + for (;;) { + c = getc(fd); + if (c == EOF) + goto bad; + if (c == '.' && bol) { /* .directive */ + if (token(fd, id, MAXID, ".directive") == EOF) + goto bad; + if (strcasecmp(id, what) == 0) + break; + continue; + } + if (c == '\\') { /* escape next character */ + c = getc(fd); + if (c == EOF) + goto bad; + } + bol = (c == '\n'); + if (bol) + lineno++; + } + return 0; +bad: + warnx("EOF with no matching .%s", what); + return EOF; +} + +static int +skipws(FILE *fd) +{ + int c, i; + + i = 0; + while ((c = getc(fd)) != EOF && isblank(c)) + i++; + if (c != EOF) + ungetc(c, fd); + if (i != 0) + bol = 0; + return 0; +} + +static void +setmode(int mode) +{ + EEPROM_POWER_EXPN_5112 *exp; + + curmode = mode; + curchan = -1; + curctl = -1; + curpdgain = -1; + curlpdgain = -1; + curpcdac = -1; + switch (curmode) { + case headerInfo11A: + pPowerInfo = eeprom.ee_trgtPwr_11a; + pDataPerChannel = eeprom.ee_dataPerChannel11a; + break; + case headerInfo11B: + pPowerInfo = eeprom.ee_trgtPwr_11b; + pDataPerChannel = eeprom.ee_dataPerChannel11b; + break; + case headerInfo11G: + pPowerInfo = eeprom.ee_trgtPwr_11g; + pDataPerChannel = eeprom.ee_dataPerChannel11g; + break; + } + if (IS_VERS(<, AR_EEPROM_VER4_0)) /* nothing to do */ + return; + if (IS_VERS(<, AR_EEPROM_VER5_0)) { + exp = &eeprom.ee_modePowerArray5112[curmode]; + /* fetch indirect data*/ + atd.ad_id = HAL_DIAG_EEPROM_EXP_11A+curmode; + atd.ad_out_size = roundup( + sizeof(u_int16_t) * exp->numChannels, sizeof(u_int32_t)) + + sizeof(EXPN_DATA_PER_CHANNEL_5112) * exp->numChannels; + atd.ad_out_data = (caddr_t) malloc(atd.ad_out_size); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + exp->pChannels = (void *) atd.ad_out_data; + exp->pDataPerChannel = (void *)((char *)atd.ad_out_data + + roundup(sizeof(u_int16_t) * exp->numChannels, sizeof(u_int32_t))); + pExpnPower = exp; + numChannels = pExpnPower->numChannels; + if (exp->xpdMask != 0x9) { + for (singleXpd = 0; singleXpd < NUM_XPD_PER_CHANNEL; singleXpd++) + if (exp->xpdMask == (1<numChannels; + } +} + +int +nextctl(int start) +{ + int i; + + for (i = start; i < eeprom.ee_numCtls && eeprom.ee_ctl[i]; i++) { + switch (eeprom.ee_ctl[i] & 3) { + case 0: case 3: + if (curmode != headerInfo11A) + continue; + break; + case 1: + if (curmode != headerInfo11B) + continue; + break; + case 2: + if (curmode != headerInfo11G) + continue; + break; + } + return i; + } + return -1; +} + +static void +printAntennaControl(FILE *fd, int ant) +{ + fprintf(fd, "0x%02X", eeprom.ee_antennaControl[ant][curmode]); +} + +static void +printEdge(FILE *fd, int edge) +{ + const RD_EDGES_POWER *pRdEdgePwrInfo = + &eeprom.ee_rdEdgesPower[curctl*NUM_EDGES]; + + if (pRdEdgePwrInfo[edge].rdEdge == 0) + fprintf(fd, " -- "); + else + fprintf(fd, "%04d", pRdEdgePwrInfo[edge].rdEdge); +} + +static void +printEdgePower(FILE *fd, int edge) +{ + const RD_EDGES_POWER *pRdEdgePwrInfo = + &eeprom.ee_rdEdgesPower[curctl*NUM_EDGES]; + + if (pRdEdgePwrInfo[edge].rdEdge == 0) + fprintf(fd, " -- "); + else + fprintf(fd, "%2d.%d", + pRdEdgePwrInfo[edge].twice_rdEdgePower / 2, + (pRdEdgePwrInfo[edge].twice_rdEdgePower % 2) * 5); +} + +static void +printEdgeFlag(FILE *fd, int edge) +{ + const RD_EDGES_POWER *pRdEdgePwrInfo = + &eeprom.ee_rdEdgesPower[curctl*NUM_EDGES]; + + if (pRdEdgePwrInfo[edge].rdEdge == 0) + fprintf(fd, "--"); + else + fprintf(fd, " %1d", pRdEdgePwrInfo[edge].flag); +} + +static int16_t +getMaxPowerV5(const RAW_DATA_PER_CHANNEL_2413 *data) +{ + uint32_t i; + uint16_t numVpd; + + for (i = 0; i < MAX_NUM_PDGAINS_PER_CHANNEL; i++) { + numVpd = data->pDataPerPDGain[i].numVpd; + if (numVpd > 0) + return data->pDataPerPDGain[i].pwr_t4[numVpd-1]; + } + return 0; +} + +static void +printQuarterDbmPower(FILE *fd, int16_t power25dBm) +{ + fprintf(fd, "%2d.%02d", power25dBm / 4, (power25dBm % 4) * 25); +} + +static void +printHalfDbmPower(FILE *fd, int16_t power5dBm) +{ + fprintf(fd, "%2d.%d", power5dBm / 2, (power5dBm % 2) * 5); +} + +static void +printVpd(FILE *fd, int vpd) +{ + fprintf(fd, "[%3d]", vpd); +} + +static void +printPcdacValue(FILE *fd, int v) +{ + fprintf(fd, "%2d.%02d", v / EEP_SCALE, v % EEP_SCALE); +} + +static void +undef(const char *what) +{ + warnx("%s undefined for version %d.%d format EEPROM", what, + eeprom.ee_version >> 12, eeprom.ee_version & 0xfff); +} + +static int +pdgain(int lpdgain) +{ + uint32_t mask; + int i, l = lpdgain; + + if (IS_VERS(<, AR_EEPROM_VER5_0)) + mask = pExpnPower->xpdMask; + else + mask = pRaw->xpd_mask; + for (i = 0; mask != 0; mask >>= 1, i++) + if ((mask & 1) && l-- == 0) + return i; + warnx("can't find logical pdgain %d", lpdgain); + return -1; +} + +#define COUNTRY_ERD_FLAG 0x8000 +#define WORLDWIDE_ROAMING_FLAG 0x4000 + +void +eevar(FILE *fd, const char *var) +{ +#define streq(a,b) (strcasecmp(a,b) == 0) +#define strneq(a,b,n) (strncasecmp(a,b,n) == 0) + if (streq(var, "mode")) { + fprintf(fd, "%s", + curmode == headerInfo11A ? "11a" : + curmode == headerInfo11B ? "11b" : + curmode == headerInfo11G ? "11g" : "???"); + } else if (streq(var, "version")) { + fprintf(fd, "%04x", eeprom.ee_version); + } else if (streq(var, "V_major")) { + fprintf(fd, "%2d", eeprom.ee_version >> 12); + } else if (streq(var, "V_minor")) { + fprintf(fd, "%2d", eeprom.ee_version & 0xfff); + } else if (streq(var, "earStart")) { + fprintf(fd, "%03x", eeprom.ee_earStart); + } else if (streq(var, "tpStart")) { + fprintf(fd, "%03x", eeprom.ee_targetPowersStart); + } else if (streq(var, "eepMap")) { + fprintf(fd, "%3d", eeprom.ee_eepMap); + } else if (streq(var, "exist32KHzCrystal")) { + fprintf(fd, "%3d", eeprom.ee_exist32kHzCrystal); + } else if (streq(var, "eepMap2PowerCalStart")) { + fprintf(fd , "%3d", eeprom.ee_eepMap2PowerCalStart); + } else if (streq(var, "Amode")) { + fprintf(fd , "%1d", eeprom.ee_Amode); + } else if (streq(var, "Bmode")) { + fprintf(fd , "%1d", eeprom.ee_Bmode); + } else if (streq(var, "Gmode")) { + fprintf(fd , "%1d", eeprom.ee_Gmode); + } else if (streq(var, "regdomain")) { + if ((eeprom.ee_regdomain & COUNTRY_ERD_FLAG) == 0) + fprintf(fd, "%03X ", eeprom.ee_regdomain >> 15); + else + fprintf(fd, "%-3dC", eeprom.ee_regdomain & 0xfff); + } else if (streq(var, "turbo2Disable")) { + fprintf(fd, "%1d", eeprom.ee_turbo2Disable); + } else if (streq(var, "turbo5Disable")) { + fprintf(fd, "%1d", eeprom.ee_turbo5Disable); + } else if (streq(var, "rfKill")) { + fprintf(fd, "%1d", eeprom.ee_rfKill); + } else if (streq(var, "disableXr5")) { + fprintf(fd, "%1d", eeprom.ee_disableXr5); + } else if (streq(var, "disableXr2")) { + fprintf(fd, "%1d", eeprom.ee_disableXr2); + } else if (streq(var, "turbo2WMaxPower5")) { + fprintf(fd, "%2d", eeprom.ee_turbo2WMaxPower5); + } else if (streq(var, "cckOfdmDelta")) { + fprintf(fd, "%2d", eeprom.ee_cckOfdmPwrDelta); + } else if (streq(var, "gainI")) { + fprintf(fd, "%2d", eeprom.ee_gainI[curmode]); + } else if (streq(var, "WWR")) { + fprintf(fd, "%1x", + (eeprom.ee_regdomain & WORLDWIDE_ROAMING_FLAG) != 0); + } else if (streq(var, "falseDetectBackoff")) { + fprintf(fd, "0x%02x", eeprom.ee_falseDetectBackoff[curmode]); + } else if (streq(var, "deviceType")) { + fprintf(fd, "%1x", eeprom.ee_deviceType); + } else if (streq(var, "switchSettling")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "0x%02x", eeprom.ee_switchSettling[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].switchSettling); + } else if (streq(var, "adcDesiredSize")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "%2d", eeprom.ee_adcDesiredSize[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].adcDesiredSize); + } else if (streq(var, "xlnaGain")) { + fprintf(fd, "0x%02x", eeprom.ee_xlnaGain[curmode]); + } else if (streq(var, "txEndToXLNAOn")) { + fprintf(fd, "0x%02x", eeprom.ee_txEndToXLNAOn[curmode]); + } else if (streq(var, "thresh62")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "0x%02x", eeprom.ee_thresh62[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].thresh62); + } else if (streq(var, "txEndToRxOn")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].txEndToRxOn); + } else if (streq(var, "txEndToXPAOff")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "0x%02x", eeprom.ee_txEndToXPAOff[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].txEndToXpaOff); + } else if (streq(var, "txFrameToXPAOn")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "0x%02x", eeprom.ee_txFrameToXPAOn[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].txEndToRxOn); + } else if (streq(var, "pgaDesiredSize")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "%2d", eeprom.ee_pgaDesiredSize[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].pgaDesiredSize); + } else if (streq(var, "noiseFloorThresh")) { + fprintf(fd, "%3d", eeprom.ee_noiseFloorThresh[curmode]); + } else if (strneq(var, "noiseFloorThreshCh", 18)) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].noiseFloorThreshCh[atoi(var+18)]); + } else if (strneq(var, "xlnaGainCh", 10)) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].xlnaGainCh[atoi(var+10)]); + } else if (streq(var, "xgain")) { + fprintf(fd, "0x%02x", eeprom.ee_xgain[curmode]); + } else if (streq(var, "xpd")) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) + fprintf(fd, "%1d", eeprom.ee_xpd[curmode]); + else + fprintf(fd, "%3d", eepromN.modalHeader[curmode].xpd); + } else if (streq(var, "txrxAtten")) { + fprintf(fd, "0x%02x", eeprom.ee_txrxAtten[curmode]); + } else if (streq(var, "capField")) { + fprintf(fd, "0x%04X", eeprom.ee_capField); + } else if (streq(var, "txrxAttenTurbo")) { + fprintf(fd, "0x%02x", + eeprom.ee_txrxAtten[curmode != headerInfo11A]); + } else if (streq(var, "switchSettlingTurbo")) { + fprintf(fd, "0x%02X", + eeprom.ee_switchSettlingTurbo[curmode != headerInfo11A]); + } else if (streq(var, "adcDesiredSizeTurbo")) { + fprintf(fd, "%2d", + eeprom.ee_adcDesiredSizeTurbo[curmode != headerInfo11A]); + } else if (streq(var, "pgaDesiredSizeTurbo")) { + fprintf(fd, "%2d", + eeprom.ee_pgaDesiredSizeTurbo[curmode != headerInfo11A]); + } else if (streq(var, "rxtxMarginTurbo")) { + fprintf(fd, "0x%02x", + eeprom.ee_rxtxMarginTurbo[curmode != headerInfo11A]); + } else if (strneq(var, "antennaControl", 14)) { + printAntennaControl(fd, atoi(var+14)); + } else if (strneq(var, "antCtrlChain", 12)) { + fprintf(fd, "0x%08X", + eepromN.modalHeader[curmode].antCtrlChain[atoi(var+12)]); + } else if (strneq(var, "antGainCh", 9)) { + fprintf(fd, "%3d", + eepromN.modalHeader[curmode].antennaGainCh[atoi(var+9)]); + } else if (strneq(var, "txRxAttenCh", 11)) { + fprintf(fd, "%3d", + eepromN.modalHeader[curmode].txRxAttenCh[atoi(var+11)]); + } else if (strneq(var, "rxTxMarginCh", 12)) { + fprintf(fd, "%3d", + eepromN.modalHeader[curmode].rxTxMarginCh[atoi(var+12)]); + } else if (streq(var, "xpdGain")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].xpdGain); + } else if (strneq(var, "iqCalICh", 8)) { + fprintf(fd, "%3d", + eepromN.modalHeader[curmode].iqCalICh[atoi(var+8)]); + } else if (strneq(var, "iqCalQCh", 8)) { + fprintf(fd, "%3d", + eepromN.modalHeader[curmode].iqCalQCh[atoi(var+8)]); + } else if (streq(var, "pdGainOverlap")) { + printHalfDbmPower(fd, eepromN.modalHeader[curmode].pdGainOverlap); + } else if (streq(var, "ob1")) { + fprintf(fd, "%1d", eeprom.ee_ob1); + } else if (streq(var, "ob2")) { + fprintf(fd, "%1d", eeprom.ee_ob2); + } else if (streq(var, "ob3")) { + fprintf(fd, "%1d", eeprom.ee_ob3); + } else if (streq(var, "ob4")) { + fprintf(fd, "%1d", eeprom.ee_ob4); + } else if (streq(var, "db1")) { + fprintf(fd, "%1d", eeprom.ee_db1); + } else if (streq(var, "db2")) { + fprintf(fd, "%1d", eeprom.ee_db2); + } else if (streq(var, "db3")) { + fprintf(fd, "%1d", eeprom.ee_db3); + } else if (streq(var, "db4")) { + fprintf(fd, "%1d", eeprom.ee_db4); + } else if (streq(var, "obFor24")) { + fprintf(fd, "%1d", eeprom.ee_obFor24); + } else if (streq(var, "ob2GHz0")) { + fprintf(fd, "%1d", eeprom.ee_ob2GHz[0]); + } else if (streq(var, "dbFor24")) { + fprintf(fd, "%1d", eeprom.ee_dbFor24); + } else if (streq(var, "db2GHz0")) { + fprintf(fd, "%1d", eeprom.ee_db2GHz[0]); + } else if (streq(var, "obFor24g")) { + fprintf(fd, "%1d", eeprom.ee_obFor24g); + } else if (streq(var, "ob2GHz1")) { + fprintf(fd, "%1d", eeprom.ee_ob2GHz[1]); + } else if (streq(var, "dbFor24g")) { + fprintf(fd, "%1d", eeprom.ee_dbFor24g); + } else if (streq(var, "db2GHz1")) { + fprintf(fd, "%1d", eeprom.ee_db2GHz[1]); + } else if (streq(var, "ob")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].ob); + } else if (streq(var, "db")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].db); + } else if (streq(var, "xpaBiasLvl")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].xpaBiasLvl); + } else if (streq(var, "pwrDecreaseFor2Chain")) { + printHalfDbmPower(fd, eepromN.modalHeader[curmode].pwrDecreaseFor2Chain); + } else if (streq(var, "pwrDecreaseFor3Chain")) { + printHalfDbmPower(fd, eepromN.modalHeader[curmode].pwrDecreaseFor3Chain); + } else if (streq(var, "txFrameToDataStart")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].txFrameToDataStart); + } else if (streq(var, "txFrameToPaOn")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].txFrameToPaOn); + } else if (streq(var, "ht40PowerIncForPdadc")) { + fprintf(fd, "%3d", eepromN.modalHeader[curmode].ht40PowerIncForPdadc); + } else if (streq(var, "checksum")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.checksum); + } else if (streq(var, "length")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.length); + } else if (streq(var, "regDmn0")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.regDmn[0]); + } else if (streq(var, "regDmn1")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.regDmn[1]); + } else if (streq(var, "txMask")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.txMask); + } else if (streq(var, "rxMask")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.rxMask); + } else if (streq(var, "rfSilent")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.rfSilent); + } else if (streq(var, "btOptions")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.blueToothOptions); + } else if (streq(var, "deviceCap")) { + fprintf(fd, "0x%04X", eepromN.baseEepHeader.deviceCap); + } else if (strneq(var, "macaddr", 7)) { + fprintf(fd, "%02X", + eepromN.baseEepHeader.macAddr[atoi(var+7)]); + } else if (streq(var, "opCapFlags")) { + fprintf(fd, "0x%02X", eepromN.baseEepHeader.opCapFlags); + } else if (streq(var, "eepMisc")) { + fprintf(fd, "0x%02X", eepromN.baseEepHeader.eepMisc); + } else if (strneq(var, "binBuildNumber", 14)) { + fprintf(fd, "%3d", + (eepromN.baseEepHeader.binBuildNumber >> (8*atoi(var+14))) + & 0xff); + } else if (strneq(var, "custData", 8)) { + fprintf(fd, "%2.2X", eepromN.custData[atoi(var+8)]); + } else if (streq(var, "xpd_mask")) { + if (IS_VERS(<, AR_EEPROM_VER5_0)) + fprintf(fd, "0x%02x", pExpnPower->xpdMask); + else + fprintf(fd, "0x%02x", pRaw->xpd_mask); + } else if (streq(var, "numChannels")) { + if (IS_VERS(<, AR_EEPROM_VER5_0)) + fprintf(fd, "%2d", pExpnPower->numChannels); + else + fprintf(fd, "%2d", pRaw->numChannels); + } else if (streq(var, "freq")) { + if (IS_VERS(<, AR_EEPROM_VER5_0)) + fprintf(fd, "%4d", pExpnPower->pChannels[curchan]); + else + fprintf(fd, "%4d", pRaw->pChannels[curchan]); + } else if (streq(var, "maxpow")) { + int16_t maxPower_t4; + if (IS_VERS(<, AR_EEPROM_VER5_0)) { + maxPower_t4 = pExpnPower->pDataPerChannel[curchan].maxPower_t4; + } else { + maxPower_t4 = pRaw->pDataPerChannel[curchan].maxPower_t4; + if (maxPower_t4 == 0) + maxPower_t4 = getMaxPowerV5(&pRaw->pDataPerChannel[curchan]); + } + printQuarterDbmPower(fd, maxPower_t4); + } else if (streq(var, "pd_gain")) { + fprintf(fd, "%4d", pRaw->pDataPerChannel[curchan]. + pDataPerPDGain[curpdgain].pd_gain); + } else if (strneq(var, "maxpwr", 6)) { + int vpd = atoi(var+6); + if (vpd < pRaw->pDataPerChannel[curchan].pDataPerPDGain[curpdgain].numVpd) + printQuarterDbmPower(fd, pRaw->pDataPerChannel[curchan]. + pDataPerPDGain[curpdgain].pwr_t4[vpd]); + else + fprintf(fd, " "); + } else if (strneq(var, "pwr_t4_", 7)) { + printQuarterDbmPower(fd, pExpnPower->pDataPerChannel[curchan]. + pDataPerXPD[singleXpd].pwr_t4[atoi(var+7)]); + } else if (strneq(var, "Vpd", 3)) { + int vpd = atoi(var+3); + if (vpd < pRaw->pDataPerChannel[curchan].pDataPerPDGain[curpdgain].numVpd) + printVpd(fd, pRaw->pDataPerChannel[curchan]. + pDataPerPDGain[curpdgain].Vpd[vpd]); + else + fprintf(fd, " "); + } else if (streq(var, "CTL")) { + fprintf(fd, "0x%2x", eeprom.ee_ctl[curctl] & 0xff); + } else if (streq(var, "ctlType")) { + static const char *ctlType[16] = { + "11a base", "11b", "11g", "11a TURBO", "108g", + "2GHT20", "5GHT20", "2GHT40", "5GHT40", + "0x9", "0xa", "0xb", "0xc", "0xd", "0xe", "0xf", + }; + fprintf(fd, "%8s", ctlType[eeprom.ee_ctl[curctl] & CTL_MODE_M]); + } else if (streq(var, "ctlRD")) { + static const char *ctlRD[8] = { + "0x00", " FCC", "0x20", "ETSI", + " MKK", "0x50", "0x60", "0x70" + }; + fprintf(fd, "%s", ctlRD[(eeprom.ee_ctl[curctl] >> 4) & 7]); + } else if (strneq(var, "rdEdgePower", 11)) { + printEdgePower(fd, atoi(var+11)); + } else if (strneq(var, "rdEdgeFlag", 10)) { + printEdgeFlag(fd, atoi(var+10)); + } else if (strneq(var, "rdEdge", 6)) { + printEdge(fd, atoi(var+6)); + } else if (strneq(var, "testChannel", 11)) { + fprintf(fd, "%4d", pPowerInfo[atoi(var+11)].testChannel); + } else if (strneq(var, "pwr6_24_", 8)) { + printHalfDbmPower(fd, pPowerInfo[atoi(var+8)].twicePwr6_24); + } else if (strneq(var, "pwr36_", 6)) { + printHalfDbmPower(fd, pPowerInfo[atoi(var+6)].twicePwr36); + } else if (strneq(var, "pwr48_", 6)) { + printHalfDbmPower(fd, pPowerInfo[atoi(var+6)].twicePwr48); + } else if (strneq(var, "pwr54_", 6)) { + printHalfDbmPower(fd, pPowerInfo[atoi(var+6)].twicePwr54); + } else if (strneq(var, "channelValue", 12)) { + fprintf(fd, "%4d", pDataPerChannel[atoi(var+12)].channelValue); + } else if (strneq(var, "pcdacMin", 8)) { + fprintf(fd, "%02d", pDataPerChannel[atoi(var+8)].pcdacMin); + } else if (strneq(var, "pcdacMax", 8)) { + fprintf(fd, "%02d", pDataPerChannel[atoi(var+8)].pcdacMax); + } else if (strneq(var, "pcdac", 5)) { + if (IS_VERS(<, AR_EEPROM_VER4_0)) { + fprintf(fd, "%02d", pDataPerChannel[atoi(var+5)]. + PcdacValues[curpcdac]); + } else if (IS_VERS(<, AR_EEPROM_VER5_0)) { + fprintf(fd, "%02d", + pExpnPower->pDataPerChannel[curchan]. + pDataPerXPD[singleXpd].pcdac[atoi(var+5)]); + } else + undef("pcdac"); + } else if (strneq(var, "pwrValue", 8)) { + printPcdacValue(fd, + pDataPerChannel[atoi(var+8)].PwrValues[curpcdac]); + } else if (streq(var, "singleXpd")) { + fprintf(fd, "%2d", singleXpd); + } else + warnx("line %u, unknown EEPROM variable \"%s\"", lineno, var); +#undef strneq +#undef streq +} + +static void +ifmode(FILE *ftemplate, const char *mode) +{ + if (strcasecmp(mode, "11a") == 0) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) { + if (eeprom.ee_Amode) + setmode(headerInfo11A); + else + skipto(ftemplate, "endmode"); + return; + } + if (IS_VERS(>=, AR_EEPROM_VER14_2)) { + if (eepromN.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) + setmode(headerInfo11A); + else + skipto(ftemplate, "endmode"); + return; + } + } else if (strcasecmp(mode, "11g") == 0) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) { + if (eeprom.ee_Gmode) + setmode(headerInfo11G); + else + skipto(ftemplate, "endmode"); + return; + } + if (IS_VERS(>=, AR_EEPROM_VER14_2)) { + if (eepromN.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) + setmode(headerInfo11B); /* NB: 2.4GHz */ + else + skipto(ftemplate, "endmode"); + return; + } + } else if (strcasecmp(mode, "11b") == 0) { + if (IS_VERS(<, AR_EEPROM_VER14_2)) { + if (eeprom.ee_Bmode) + setmode(headerInfo11B); + else + skipto(ftemplate, "endmode"); + return; + } + } + warnx("line %d, unknown/unexpected mode \"%s\" ignored", + lineno, mode); + skipto(ftemplate, "endmode"); +} + +static void +parseTemplate(FILE *ftemplate, FILE *fd) +{ + int c, i; + char id[MAXID]; + long forchan, forpdgain, forctl, forpcdac; + + lineno = 1; + bol = 1; + while ((c = getc(ftemplate)) != EOF) { + if (c == '#') { /* comment */ + skiptoeol: + while ((c = getc(ftemplate)) != EOF && c != '\n') + ; + if (c == EOF) + return; + lineno++; + bol = 1; + continue; + } + if (c == '.' && bol) { /* .directive */ + if (token(ftemplate, id, MAXID, ".directive") == EOF) + return; + /* process directive */ + if (strcasecmp(id, "ifmode") == 0) { + skipws(ftemplate); + if (token(ftemplate, id, MAXID, "id") == EOF) + return; + ifmode(ftemplate, id); + } else if (strcasecmp(id, "endmode") == 0) { + /* XXX free malloc'd indirect data */ + curmode = -1; /* NB: undefined */ + } else if (strcasecmp(id, "forchan") == 0) { + forchan = ftell(ftemplate) - sizeof("forchan"); + if (curchan == -1) + curchan = 0; + } else if (strcasecmp(id, "endforchan") == 0) { + if (++curchan < numChannels) + fseek(ftemplate, forchan, SEEK_SET); + else + curchan = -1; + } else if (strcasecmp(id, "ifpdgain") == 0) { + skipws(ftemplate); + if (token(ftemplate, id, MAXID, "pdgain") == EOF) + return; + curlpdgain = strtoul(id, NULL, 0); + if (curlpdgain >= pRaw->pDataPerChannel[curchan].numPdGains) { + skipto(ftemplate, "endpdgain"); + curlpdgain = -1; + } else + curpdgain = pdgain(curlpdgain); + } else if (strcasecmp(id, "endpdgain") == 0) { + curlpdgain = curpdgain = -1; + } else if (strcasecmp(id, "forpdgain") == 0) { + forpdgain = ftell(ftemplate) - sizeof("forpdgain"); + if (curlpdgain == -1) { + skipws(ftemplate); + if (token(ftemplate, id, MAXID, "pdgain") == EOF) + return; + curlpdgain = strtoul(id, NULL, 0); + if (curlpdgain >= pRaw->pDataPerChannel[curchan].numPdGains) { + skipto(ftemplate, "endforpdgain"); + curlpdgain = -1; + } else + curpdgain = pdgain(curlpdgain); + } + } else if (strcasecmp(id, "endforpdgain") == 0) { + if (++curpdgain < pRaw->pDataPerChannel[curchan].numPdGains) + fseek(ftemplate, forpdgain, SEEK_SET); + else + curpdgain = -1; + } else if (strcasecmp(id, "forpcdac") == 0) { + forpcdac = ftell(ftemplate) - sizeof("forpcdac"); + if (curpcdac == -1) + curpcdac = 0; + } else if (strcasecmp(id, "endforpcdac") == 0) { + if (++curpcdac < pDataPerChannel[0].numPcdacValues) + fseek(ftemplate, forpcdac, SEEK_SET); + else + curpcdac = -1; + } else if (strcasecmp(id, "forctl") == 0) { + forctl = ftell(ftemplate) - sizeof("forchan"); + if (curctl == -1) + curctl = nextctl(0); + } else if (strcasecmp(id, "endforctl") == 0) { + curctl = nextctl(curctl+1); + if (curctl != -1) + fseek(ftemplate, forctl, SEEK_SET); + } else { + warnx("line %d, unknown directive %s ignored", + lineno, id); + } + goto skiptoeol; + } + if (c == '$') { /* $variable reference */ + if (token(ftemplate, id, MAXID, "$var") == EOF) + return; + /* XXX not valid if variable depends on curmode */ + eevar(fd, id); + continue; + } + if (c == '\\') { /* escape next character */ + c = getc(ftemplate); + if (c == EOF) + return; + } + fputc(c, fd); + bol = (c == '\n'); + if (bol) + lineno++; + } +} diff --git a/tools/tools/ath/athprom/eeprom-14 b/tools/tools/ath/athprom/eeprom-14 new file mode 100644 index 000000000000..ef2b1c69dd03 --- /dev/null +++ b/tools/tools/ath/athprom/eeprom-14 @@ -0,0 +1,120 @@ +# $FreeBSD$ +# +# v14 format EEPROM template (AR5416 and later 11n parts) +# + |===================== Header Information ====================| + | Major Version $V_major | Minor Version $V_minor | + |-------------------------------------------------------------| + | Checksum $checksum | Length $length | + | RegDomain 1 $regDmn0 | RegDomain 2 $regDmn1 | + | TX Mask $txMask | RX Mask $rxMask | + | rfSilent $rfSilent | btOptions $btOptions | + | deviceCap $deviceCap | | + | MacAddress: $macaddr0:$macaddr1:$macaddr2:$macaddr3:$macaddr4:$macaddr5 | + | OpFlags: [$opCapFlags] 11A 1, 11G 1 | + | eepMisc: [$eepMisc] endian 0 | + |-------------------------------------------------------------| + | Customer Data in hex | + |= $custData0 $custData1 $custData2 $custData3 $custData4 $custData5 $custData6 $custData7 $custData8 $custData9 $custData10 $custData11 $custData12 $custData13 $custData14 $custData15 =| + |= $custData16 $custData17 $custData18 $custData19 $custData20 $custData21 $custData22 $custData23 $custData24 $custData25 $custData26 $custData27 $custData28 $custData29 $custData30 $custData31 =| + |= $custData32 $custData33 $custData34 $custData35 $custData36 $custData37 $custData38 $custData39 $custData40 $custData41 $custData42 $custData43 $custData44 $custData45 $custData46 $custData47 =| + |= $custData48 $custData49 $custData50 $custData51 $custData52 $custData53 $custData54 $custData55 $custData56 $custData57 $custData58 $custData59 $custData60 $custData61 $custData62 $custData63 =| + |=============================================================| + +.ifmode 11a + |=========== 5GHz Modal Header ===========| + | Ant Chain 0 $antCtrlChain0 | + | Ant Chain 1 $antCtrlChain1 | + | Ant Chain 2 $antCtrlChain2 | + | Ant Chain common 0x00001120 | + | Antenna Gain Chain 0 $antGainCh0 | + | Antenna Gain Chain 1 $antGainCh1 | + | Antenna Gain Chain 2 $antGainCh2 | + | Switch Settling $switchSettling | + | TxRxAttenuation Ch 0 $txRxAttenCh0 | + | TxRxAttenuation Ch 1 $txRxAttenCh1 | + | TxRxAttenuation Ch 2 $txRxAttenCh2 | + | RxTxMargin Chain 0 $rxTxMarginCh0 | + | RxTxMargin Chain 1 $rxTxMarginCh1 | + | RxTxMargin Chain 2 $rxTxMarginCh2 | + | adc desired size $adcDesiredSize | + | pga desired size $pgaDesiredSize | + | xlna gain Chain 0 $xlnaGainCh0 | + | xlna gain Chain 1 $xlnaGainCh1 | + | xlna gain Chain 2 $xlnaGainCh2 | + | tx end to xpa off $txEndToXPAOff | + | tx end to rx on $txEndToRxOn | + | tx frame to xpa on $txFrameToXPAOn | + | thresh62 $thresh62 | + | noise floor thres 0 $noiseFloorThreshCh0 | + | noise floor thres 1 $noiseFloorThreshCh1 | + | noise floor thres 2 $noiseFloorThreshCh2 | + | Xpd Gain Mask $xpdGain | + | Xpd extern $xpd | + | IQ Cal I, Q Chain 0 $iqCalICh0, $iqCalQCh0 | + | IQ Cal I, Q Chain 1 $iqCalICh1, $iqCalQCh1 | + | IQ Cal I, Q Chain 2 $iqCalICh2, $iqCalQCh2 | + | pdGain Overlap $pdGainOverlap dB | + | Analog Output Bias (ob) $ob | + | Analog Driver Bias (db) $db | + | Xpa bias level $xpaBiasLvl | + | pwr dec 2 chain $pwrDecreaseFor2Chain dB | + | pwr dec 3 chain $pwrDecreaseFor3Chain dB | + | txFrameToDataStart $txFrameToDataStart | + | txFrameToPaOn $txFrameToPaOn | + | ht40PowerIncForPdadc $ht40PowerIncForPdadc | + |=========================================| + +============================Target Power Info=============================== +| rate | $testChannel0 | $testChannel1 | $testChannel2 | $testChannel3 | +|==============|==============|==============|==============|==============| +| 6-24 | $pwr6_24_0 | $pwr6_24_1 | $pwr6_24_2 | $pwr6_24_3 | +| 36 | $pwr36_0 | $pwr36_1 | $pwr36_2 | $pwr36_3 | +| 48 | $pwr48_0 | $pwr48_1 | $pwr48_2 | $pwr48_3 | +| 54 | $pwr54_0 | $pwr54_1 | $pwr54_2 | $pwr54_3 | +|==============|==============|==============|==============|==============| +| rate | $testChannel4 | $testChannel5 | $testChannel6 | $testChannel7 | +|==============|==============|==============|==============|==============| +| 6-24 | $pwr6_24_4 | $pwr6_24_5 | $pwr6_24_6 | $pwr6_24_7 | +| 36 | $pwr36_4 | $pwr36_5 | $pwr36_6 | $pwr36_7 | +| 48 | $pwr48_4 | $pwr48_5 | $pwr48_6 | $pwr48_7 | +| 54 | $pwr54_4 | $pwr54_5 | $pwr54_6 | $pwr54_7 | +|==============|==============|==============|==============|==============| + +=======================Test Group Band Edge Power======================== +.forctl +| | +| CTL: $CTL [ $ctlRD $ctlType mode ] | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | +========================================================================= +.endforctl +.endmode + +.ifmode 11g +=============Target Power Info================ +| rate | $testChannel0 | $testChannel1 | +|==============|==============|==============| +| 1 | $pwr6_24_0 | $pwr6_24_1 | +| 2 | $pwr36_0 | $pwr36_1 | +| 5.5 | $pwr48_0 | $pwr48_1 | +| 11 | $pwr54_0 | $pwr54_1 | +|==============|==============|==============| + +=======================Test Group Band Edge Power======================== +.forctl +| | +| CTL: $CTL [ $ctlRD $ctlType mode ] | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | +========================================================================= +.endforctl +.endmode diff --git a/tools/tools/ath/athprom/eeprom-3 b/tools/tools/ath/athprom/eeprom-3 new file mode 100644 index 000000000000..73c7033705d6 --- /dev/null +++ b/tools/tools/ath/athprom/eeprom-3 @@ -0,0 +1,165 @@ +# $FreeBSD$ +# +# v3 format EEPROM template +# +.ifmode 11a + =================Header Information for mode 11a=============== + | Major Version $V_major | Minor Version $V_minor | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $ob1 | OB_2 $ob2 | OB_3 $ob3 | OB_4 $ob4 | + | DB_1 $db1 | DB_2 $db2 | DB_3 $db3 | DB_4 $db4 | + =============================================================== + + =========================Calibration Information============================ + | $channelValue0 | $channelValue1 | $channelValue2 | $channelValue3 | $channelValue4 | + |==============|==============|==============|==============|==============| + |pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)| +.forpcdac + | $pcdac0 $pwrValue0 | $pcdac1 $pwrValue1 | $pcdac2 $pwrValue2 | $pcdac3 $pwrValue3 | $pcdac4 $pwrValue4 | +.endforpcdac + | | | | | | + | pcdac min $pcdacMin0 | pcdac min $pcdacMin1 | pcdac min $pcdacMin2 | pcdac min $pcdacMin3 | pcdac min $pcdacMin4 | + | pcdac max $pcdacMax0 | pcdac max $pcdacMax1 | pcdac max $pcdacMax2 | pcdac max $pcdacMax3 | pcdac max $pcdacMax4 | + |==============|==============|==============|==============|==============| + | $channelValue5 | $channelValue6 | $channelValue7 | $channelValue8 | $channelValue9 | + |==============|==============|==============|==============|==============| + |pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)| +.forpcdac + | $pcdac5 $pwrValue5 | $pcdac6 $pwrValue6 | $pcdac7 $pwrValue7 | $pcdac8 $pwrValue8 | $pcdac9 $pwrValue9 | +.endforpcdac + | | | | | | + | pcdac min $pcdacMin5 | pcdac min $pcdacMin6 | pcdac min $pcdacMin7 | pcdac min $pcdacMin8 | pcdac min $pcdacMin9 | + | pcdac max $pcdacMax5 | pcdac max $pcdacMax6 | pcdac max $pcdacMax7 | pcdac max $pcdacMax8 | pcdac max $pcdacMax9 | + |==============|==============|==============|==============|==============| + + ============================Target Power Info=============================== + | rate | $testChannel0 | $testChannel1 | $testChannel2 | $testChannel3 | + |==============|==============|==============|==============|==============| + | 6-24 | $pwr6_24_0 | $pwr6_24_1 | $pwr6_24_2 | $pwr6_24_3 | + | 36 | $pwr36_0 | $pwr36_1 | $pwr36_2 | $pwr36_3 | + | 48 | $pwr48_0 | $pwr48_1 | $pwr48_2 | $pwr48_3 | + | 54 | $pwr54_0 | $pwr54_1 | $pwr54_2 | $pwr54_3 | + |==============|==============|==============|==============|==============| + | rate | $testChannel4 | $testChannel5 | $testChannel6 | $testChannel7 | + |==============|==============|==============|==============|==============| + | 6-24 | $pwr6_24_4 | $pwr6_24_5 | $pwr6_24_6 | $pwr6_24_7 | + | 36 | $pwr36_4 | $pwr36_5 | $pwr36_6 | $pwr36_7 | + | 48 | $pwr48_4 | $pwr48_5 | $pwr48_6 | $pwr48_7 | + | 54 | $pwr54_4 | $pwr54_5 | $pwr54_6 | $pwr54_7 | + |==============|==============|==============|==============|==============| +.endmode + +.ifmode 11b + =================Header Information for mode 11b=============== + | Major Version $V_major | Minor Version $V_minor | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $obFor24 | B_OB $ob2GHz0 | DB_1 $dbFor24 | B_DB $db2GHz0 | + =============================================================== + + ==========Calibration Information============= + | $channelValue0 | $channelValue1 | $channelValue2 | + |==============|==============|==============| + |pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)| +.forpcdac + | $pcdac0 $pwrValue0 | $pcdac1 $pwrValue1 | $pcdac2 $pwrValue2 | +.endforpcdac + | | | | + | pcdac min $pcdacMin0 | pcdac min $pcdacMin1 | pcdac min $pcdacMin2 | + | pcdac max $pcdacMax0 | pcdac max $pcdacMax1 | pcdac max $pcdacMax2 | + |==============|==============|==============| + + =============Target Power Info================ + | rate | $testChannel0 | $testChannel1 | + |==============|==============|==============| + | 1 | $pwr6_24_0 | $pwr6_24_1 | + | 2 | $pwr36_0 | $pwr36_1 | + | 5.5 | $pwr48_0 | $pwr48_1 | + | 11 | $pwr54_0 | $pwr54_1 | + |==============|==============|==============| +.endmode + +.ifmode 11g + =================Header Information for mode 11g=============== + | Major Version $V_major | Minor Version $V_minor | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $obFor24g | B_OB $ob2GHz1 | DB_1 $dbFor24g | B_DB $db2GHz1 | + =============================================================== + + ==========Calibration Information============= + | $channelValue0 | $channelValue1 | $channelValue2 | + |==============|==============|==============| + |pcdac pwr(dBm)|pcdac pwr(dBm)|pcdac pwr(dBm)| +.forpcdac + | $pcdac0 $pwrValue0 | $pcdac1 $pwrValue1 | $pcdac2 $pwrValue2 | +.endforpcdac + | | | | + | pcdac min $pcdacMin0 | pcdac min $pcdacMin1 | pcdac min $pcdacMin2 | + | pcdac max $pcdacMax0 | pcdac max $pcdacMax1 | pcdac max $pcdacMax2 | + |==============|==============|==============| + + =============Target Power Info================ + | rate | $testChannel0 | $testChannel1 | + |==============|==============|==============| + | 1 | $pwr6_24_0 | $pwr6_24_1 | + | 2 | $pwr36_0 | $pwr36_1 | + | 5.5 | $pwr48_0 | $pwr48_1 | + | 11 | $pwr54_0 | $pwr54_1 | + |==============|==============|==============| +.endmode diff --git a/tools/tools/ath/athprom/eeprom-4 b/tools/tools/ath/athprom/eeprom-4 new file mode 100644 index 000000000000..0d4708bebc63 --- /dev/null +++ b/tools/tools/ath/athprom/eeprom-4 @@ -0,0 +1,206 @@ +# $FreeBSD$ +# +# v4 format EEPROM template +# +.ifmode 11a + =================Header Information for mode $mode=============== + | Major Version $V_major | Minor Version $V_minor | + | EAR Start $earStart | Target Power Start $tpStart | + | EEP MAP $eepMap | Enable 32 khz $exist32KHzCrystal | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | worldwide roaming $WWR | False detect backoff $falseDetectBackoff | + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $ob1 | OB_2 $ob2 | OB_3 $ob3 | OB_4 $ob4 | + | DB_1 $db1 | DB_2 $db2 | DB_3 $db3 | DB_4 $db4 | + =============================================================== + + =========5112 Power Calibration Information========== + | XPD_Gain_mask $xpd_mask | Number of channels $numChannels | + | XPD_GAIN $singleXpd | | + |======|========|========|========|========|========| + | freq | pwr1 | pwr2 | pwr3 | pwr4 | maxPow | + | | [pcd] | [pcd] | [pcd] | [pcd] | | + |======|========|========|========|========|========| +.forchan + | $freq | $pwr_t4_0 | $pwr_t4_1 | $pwr_t4_2 | $pwr_t4_3 | $maxpow | + | | [$pcdac0] | [$pcdac1] | [$pcdac2] | [$pcdac3] | | + |======|========|========|========|========|========| +.endforchan + + ============================Target Power Info=============================== + | rate | $testChannel0 | $testChannel1 | $testChannel2 | $testChannel3 | + |==============|==============|==============|==============|==============| + | 6-24 | $pwr6_24_0 | $pwr6_24_1 | $pwr6_24_2 | $pwr6_24_3 | + | 36 | $pwr36_0 | $pwr36_1 | $pwr36_2 | $pwr36_3 | + | 48 | $pwr48_0 | $pwr48_1 | $pwr48_2 | $pwr48_3 | + | 54 | $pwr54_0 | $pwr54_1 | $pwr54_2 | $pwr54_3 | + |==============|==============|==============|==============|==============| + | rate | $testChannel4 | $testChannel5 | $testChannel6 | $testChannel7 | + |==============|==============|==============|==============|==============| + | 6-24 | $pwr6_24_4 | $pwr6_24_5 | $pwr6_24_6 | $pwr6_24_7 | + | 36 | $pwr36_4 | $pwr36_5 | $pwr36_6 | $pwr36_7 | + | 48 | $pwr48_4 | $pwr48_5 | $pwr48_6 | $pwr48_7 | + | 54 | $pwr54_4 | $pwr54_5 | $pwr54_6 | $pwr54_7 | + |==============|==============|==============|==============|==============| + + =======================Test Group Band Edge Power======================== +.forctl + | | + | CTL: $CTL [ $ctlRD $ctlType mode ] | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | + ========================================================================= +.endforctl +.endmode + +.ifmode 11b + =================Header Information for mode $mode=============== + | Major Version $V_major | Minor Version $V_minor | + | EAR Start $earStart | Target Power Start $tpStart | + | EEP MAP $eepMap | Enable 32 khz $exist32KHzCrystal | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | worldwide roaming $WWR | False detect backoff $falseDetectBackoff | + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $obFor24 | B_OB $ob2GHz0 | DB_1 $dbFor24 | B_DB $db2GHz0 | + =============================================================== + + =========5112 Power Calibration Information========== + | XPD_Gain_mask $xpd_mask | Number of channels $numChannels | + | XPD_GAIN $singleXpd | | + |======|========|========|========|========|========| + | freq | pwr1 | pwr2 | pwr3 | pwr4 | maxPow | + | | [pcd] | [pcd] | [pcd] | [pcd] | | + |======|========|========|========|========|========| +.forchan + | $freq | $pwr_t4_0 | $pwr_t4_1 | $pwr_t4_2 | $pwr_t4_3 | $maxpow | + | | [$pcdac0] | [$pcdac1] | [$pcdac2] | [$pcdac3] | | + |======|========|========|========|========|========| +.endforchan + + =============Target Power Info================ + | rate | $testChannel0 | $testChannel1 | + |==============|==============|==============| + | 1 | $pwr6_24_0 | $pwr6_24_1 | + | 2 | $pwr36_0 | $pwr36_1 | + | 5.5 | $pwr48_0 | $pwr48_1 | + | 11 | $pwr54_0 | $pwr54_1 | + |==============|==============|==============| + + =======================Test Group Band Edge Power======================== +.forctl + | | + | CTL: $CTL [ $ctlRD $ctlType mode ] | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | + ========================================================================= +.endforctl +.endmode + +.ifmode 11g + =================Header Information for mode $mode=============== + | Major Version $V_major | Minor Version $V_minor | + | EAR Start $earStart | Target Power Start $tpStart | + | EEP MAP $eepMap | Enable 32 khz $exist32KHzCrystal | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | worldwide roaming $WWR | False detect backoff $falseDetectBackoff | + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $obFor24g | B_OB $ob2GHz1 | DB_1 $dbFor24g | B_DB $db2GHz1 | + =============================================================== + + =========5112 Power Calibration Information========== + | XPD_Gain_mask $xpd_mask | Number of channels $numChannels | + | XPD_GAIN $singleXpd | | + |======|========|========|========|========|========| + | freq | pwr1 | pwr2 | pwr3 | pwr4 | maxPow | + | | [pcd] | [pcd] | [pcd] | [pcd] | | + |======|========|========|========|========|========| +.forchan + | $freq | $pwr_t4_0 | $pwr_t4_1 | $pwr_t4_2 | $pwr_t4_3 | $maxpow | + | | [$pcdac0] | [$pcdac1] | [$pcdac2] | [$pcdac3] | | + |======|========|========|========|========|========| +.endforchan + + =============Target Power Info================ + | rate | $testChannel0 | $testChannel1 | + |==============|==============|==============| + | 6-24 | $pwr6_24_0 | $pwr6_24_1 | + | 35 | $pwr36_0 | $pwr36_1 | + | 48 | $pwr48_0 | $pwr48_1 | + | 54 | $pwr54_0 | $pwr54_1 | + |==============|==============|==============| + + =======================Test Group Band Edge Power======================== +.forctl + | | + | CTL: $CTL [ $ctlRD $ctlType mode ] | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | + |=======|=======|=======|=======|=======|=======|=======|=======|=======| + | flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | + ========================================================================= +.endforctl +.endmode diff --git a/tools/tools/ath/athprom/eeprom-5 b/tools/tools/ath/athprom/eeprom-5 new file mode 100644 index 000000000000..b48a42ad3e91 --- /dev/null +++ b/tools/tools/ath/athprom/eeprom-5 @@ -0,0 +1,245 @@ +# $FreeBSD$ +# +# v5 format EEPROM template +# +.ifmode 11a + =================Header Information for mode 11a=============== + | Major Version $V_major | Minor Version $V_minor | + | EAR Start $earStart | Target Power Start $tpStart | + | EEP MAP $eepMap | Enable 32 khz $exist32KHzCrystal | + | EEP Map2PowerCalStart $eepMap2PowerCalStart | | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | worldwide roaming $WWR | False detect backoff $falseDetectBackoff | + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Turbo txrx Attenuat $txrxAttenTurbo | Turbo Switch Settling $switchSettlingTurbo | + | Turbo ADC Desired Size $adcDesiredSizeTurbo | Turbo PGA Desired Size $pgaDesiredSizeTurbo | + | Turbo rxtx Margin $rxtxMarginTurbo | | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $ob1 | OB_2 $ob2 | OB_3 $ob3 | OB_4 $ob4 | + | DB_1 $db1 | DB_2 $db2 | DB_3 $db3 | DB_4 $db4 | + =============================================================== + +=========2413 Power Calibration Information=================== +| XPD_Gain_mask $xpd_mask | Number of channels $numChannels | | +|========|======|========|========|========|========|========| +| freq | pd | pwr1 | pwr2 | pwr3 | pwr4 | pwr5 | +| maxpow | gain | [Vpd] | [Vpd] | [Vpd] | [Vpd] | [Vpd] | +|========|======|========|========|========|========|========| +.forchan +.ifpdgain 0 +| $freq | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endpdgain +.ifpdgain 1 +| $maxpow | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endpdgain +.forpdgain 2 +| $maxpow | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endforpdgain +|========|======|========|========|========|========|========| +.endforchan + +============================Target Power Info=============================== +| rate | $testChannel0 | $testChannel1 | $testChannel2 | $testChannel3 | +|==============|==============|==============|==============|==============| +| 6-24 | $pwr6_24_0 | $pwr6_24_1 | $pwr6_24_2 | $pwr6_24_3 | +| 36 | $pwr36_0 | $pwr36_1 | $pwr36_2 | $pwr36_3 | +| 48 | $pwr48_0 | $pwr48_1 | $pwr48_2 | $pwr48_3 | +| 54 | $pwr54_0 | $pwr54_1 | $pwr54_2 | $pwr54_3 | +|==============|==============|==============|==============|==============| +| rate | $testChannel4 | $testChannel5 | $testChannel6 | $testChannel7 | +|==============|==============|==============|==============|==============| +| 6-24 | $pwr6_24_4 | $pwr6_24_5 | $pwr6_24_6 | $pwr6_24_7 | +| 36 | $pwr36_4 | $pwr36_5 | $pwr36_6 | $pwr36_7 | +| 48 | $pwr48_4 | $pwr48_5 | $pwr48_6 | $pwr48_7 | +| 54 | $pwr54_4 | $pwr54_5 | $pwr54_6 | $pwr54_7 | +|==============|==============|==============|==============|==============| + +=======================Test Group Band Edge Power======================== +.forctl +| | +| CTL: $CTL [ $ctlRD $ctlType mode ] | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | +========================================================================= +.endforctl +.endmode + +.ifmode 11b + =================Header Information for mode 11b=============== + | Major Version $V_major | Minor Version $V_minor | + | EAR Start $earStart | Target Power Start $tpStart | + | EEP MAP $eepMap | Enable 32 khz $exist32KHzCrystal | + | EEP Map2PowerCalStart $eepMap2PowerCalStart | | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | worldwide roaming $WWR | False detect backoff $falseDetectBackoff | + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Turbo txrx Attenuat $txrxAttenTurbo | Turbo Switch Settling $switchSettlingTurbo | + | Turbo ADC Desired Size $adcDesiredSizeTurbo | Turbo PGA Desired Size $pgaDesiredSizeTurbo | + | Turbo rxtx Margin $rxtxMarginTurbo | | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $obFor24 | B_OB $ob2GHz0 | DB_1 $dbFor24 | B_DB $db2GHz0 | + =============================================================== + +=========2413 Power Calibration Information=================== +| XPD_Gain_mask $xpd_mask | Number of channels $numChannels | | +|========|======|========|========|========|========|========| +| freq | pd | pwr1 | pwr2 | pwr3 | pwr4 | pwr5 | +| maxpow | gain | [Vpd] | [Vpd] | [Vpd] | [Vpd] | [Vpd] | +|========|======|========|========|========|========|========| +.forchan +.ifpdgain 0 +| $freq | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endpdgain +.ifpdgain 1 +| $maxpow | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endpdgain +.forpdgain 2 +| $maxpow | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endforpdgain +|========|======|========|========|========|========|========| +.endforchan + +=============Target Power Info================ +| rate | $testChannel0 | $testChannel1 | +|==============|==============|==============| +| 1 | $pwr6_24_0 | $pwr6_24_1 | +| 2 | $pwr36_0 | $pwr36_1 | +| 5.5 | $pwr48_0 | $pwr48_1 | +| 11 | $pwr54_0 | $pwr54_1 | +|==============|==============|==============| + +=======================Test Group Band Edge Power======================== +.forctl +| | +| CTL: $CTL [ $ctlRD $ctlType mode ] | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | +========================================================================= +.endforctl +.endmode + +.ifmode 11g + =================Header Information for mode 11g=============== + | Major Version $V_major | Minor Version $V_minor | + | EAR Start $earStart | Target Power Start $tpStart | + | EEP MAP $eepMap | Enable 32 khz $exist32KHzCrystal | + | EEP Map2PowerCalStart $eepMap2PowerCalStart | | + |-------------------------------------------------------------| + | A Mode $Amode | B Mode $Bmode | G Mode $Gmode | + | RegDomain $regdomain | Turbo2 Disable $turbo2Disable | Turbo5 Disable $turbo5Disable | + | RF Silent $rfKill | XR5 Disable $disableXr5 | XR2 Disable $disableXr2 | + | Turbo 2W Maximum dBm $turbo2WMaxPower5 | cckOfdmDelta(10x) $cckOfdmDelta | GainI $gainI | + |-------------------------------------------------------------| + | worldwide roaming $WWR | False detect backoff $falseDetectBackoff | + | device type $deviceType | Switch Settling Time $switchSettling | + | ADC Desired size $adcDesiredSize | XLNA Gain $xlnaGain | + | tx end to XLNA on $txEndToXLNAOn | Threashold 62 $thresh62 | + | tx end to XPA off $txEndToXPAOff | tx end to XPA on $txFrameToXPAOn | + | PGA Desired size $pgaDesiredSize | Noise Threshold $noiseFloorThresh | + | XPD Gain $xgain | XPD $xpd | + | txrx Attenuation $txrxAtten | Capabilities $capField | + | Turbo txrx Attenuat $txrxAttenTurbo | Turbo Switch Settling $switchSettlingTurbo | + | Turbo ADC Desired Size $adcDesiredSizeTurbo | Turbo PGA Desired Size $pgaDesiredSizeTurbo | + | Turbo rxtx Margin $rxtxMarginTurbo | | + | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 | + | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 | + | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 | + | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 | + | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 | + | Antenna control 10 $antennaControl10 | | + |-------------------------------------------------------------| + | OB_1 $obFor24g | B_OB $ob2GHz1 | DB_1 $dbFor24g | B_DB $db2GHz1 | + =============================================================== + +=========2413 Power Calibration Information=================== +| XPD_Gain_mask $xpd_mask | Number of channels $numChannels | | +|========|======|========|========|========|========|========| +| freq | pd | pwr1 | pwr2 | pwr3 | pwr4 | pwr5 | +| maxpow | gain | [Vpd] | [Vpd] | [Vpd] | [Vpd] | [Vpd] | +|========|======|========|========|========|========|========| +.forchan +.ifpdgain 0 +| $freq | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endpdgain +.ifpdgain 1 +| $maxpow | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endpdgain +.forpdgain 2 +| $maxpow | $pd_gain | $maxpwr0 | $maxpwr1 | $maxpwr2 | $maxpwr3 | $maxpwr4 | +| | | $Vpd0 | $Vpd1 | $Vpd2 | $Vpd3 | $Vpd4 | +.endforpdgain +|========|======|========|========|========|========|========| +.endforchan + +=============Target Power Info================ +| rate | $testChannel0 | $testChannel1 | +|==============|==============|==============| +| 6-24 | $pwr6_24_0 | $pwr6_24_1 | +| 36 | $pwr36_0 | $pwr36_1 | +| 48 | $pwr48_0 | $pwr48_1 | +| 54 | $pwr54_0 | $pwr54_1 | +|==============|==============|==============| + +=======================Test Group Band Edge Power======================== +.forctl +| | +| CTL: $CTL [ $ctlRD $ctlType mode ] | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| edge | $rdEdge0 | $rdEdge1 | $rdEdge2 | $rdEdge3 | $rdEdge4 | $rdEdge5 | $rdEdge6 | $rdEdge7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| power | $rdEdgePower0 | $rdEdgePower1 | $rdEdgePower2 | $rdEdgePower3 | $rdEdgePower4 | $rdEdgePower5 | $rdEdgePower6 | $rdEdgePower7 | +|=======|=======|=======|=======|=======|=======|=======|=======|=======| +| flag | $rdEdgeFlag0 | $rdEdgeFlag1 | $rdEdgeFlag2 | $rdEdgeFlag3 | $rdEdgeFlag4 | $rdEdgeFlag5 | $rdEdgeFlag6 | $rdEdgeFlag7 | +========================================================================= +.endforctl +.endmode diff --git a/tools/tools/ath/athregs/Makefile b/tools/tools/ath/athregs/Makefile new file mode 100644 index 000000000000..67e21d22973f --- /dev/null +++ b/tools/tools/ath/athregs/Makefile @@ -0,0 +1,13 @@ +# $FreeBSD$ + +PROG= athregs + +SRCS= dumpregs.c +SRCS+= dumpregs_5210.c +SRCS+= dumpregs_5211.c +SRCS+= dumpregs_5212.c +SRCS+= dumpregs_5416.c + +.include <../Makefile.inc> + +.include diff --git a/tools/tools/ath/athregs/dumpregs.c b/tools/tools/ath/athregs/dumpregs.c new file mode 100644 index 000000000000..8225779c08f0 --- /dev/null +++ b/tools/tools/ath/athregs/dumpregs.c @@ -0,0 +1,720 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" +/* XXX cheat, 5212 has a superset of the key table defs */ +#include "ar5212/ar5212reg.h" + +#include "dumpregs.h" + +#include +#include +#include +#include + +typedef struct { + HAL_REVS revs; + u_int32_t regdata[0xffff / sizeof(u_int32_t)]; +#define MAXREGS 5*1024 + struct dumpreg *regs[MAXREGS]; + u_int nregs; + u_int show_names : 1, + show_addrs : 1; +} dumpregs_t; +static dumpregs_t state; + +#undef OS_REG_READ +#define OS_REG_READ(ah, off) state.regdata[(off) >> 2] + +static int ath_hal_anyregs(int what); +static int ath_hal_setupregs(struct ath_diag *atd, int what); +static u_int ath_hal_setupdiagregs(const HAL_REGRANGE regs[], u_int nr); +static void ath_hal_dumpregs(FILE *fd, int what); +static void ath_hal_dumprange(FILE *fd, u_int a, u_int b); +static void ath_hal_dumpkeycache(FILE *fd, int nkeys); +static void ath_hal_dumpint(FILE *fd, int what); +static void ath_hal_dumpqcu(FILE *fd, int what); +static void ath_hal_dumpdcu(FILE *fd, int what); +static void ath_hal_dumpbb(FILE *fd, int what); + +static void +usage(void) +{ + fprintf(stderr, "usage: athregs [-i interface] [-abdkmqxz]\n"); + fprintf(stderr, "-a display all registers\n"); + fprintf(stderr, "-b display baseband registers\n"); + fprintf(stderr, "-d display DCU registers\n"); + fprintf(stderr, "-k display key cache registers\n"); + fprintf(stderr, "-m display \"MAC\" registers (default)\n"); + fprintf(stderr, "-q display QCU registers\n"); + fprintf(stderr, "-x display XR registers\n"); + fprintf(stderr, "-z display interrupt registers\n"); + fprintf(stderr, "\n"); + fprintf(stderr, "-A display register address\n"); + fprintf(stderr, "-N suppress display of register name\n"); + exit(-1); +} + +int +main(int argc, char *argv[]) +{ + struct ath_diag atd; + const char *ifname; + u_int32_t *data; + u_int32_t *dp, *ep; + int what, c, s, i; + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) + err(1, "socket"); + ifname = getenv("ATH"); + if (!ifname) + ifname = ATH_DEFAULT; + + what = 0; + state.show_addrs = 0; + state.show_names = 1; + while ((c = getopt(argc, argv, "i:aAbdkmNqxz")) != -1) + switch (c) { + case 'a': + what |= DUMP_ALL; + break; + case 'A': + state.show_addrs = 1; + break; + case 'b': + what |= DUMP_BASEBAND; + break; + case 'd': + what |= DUMP_DCU; + break; + case 'k': + what |= DUMP_KEYCACHE; + break; + case 'i': + ifname = optarg; + break; + case 'm': + what |= DUMP_BASIC; + break; + case 'N': + state.show_names = 0; + break; + case 'q': + what |= DUMP_QCU; + break; + case 'x': + what |= DUMP_XR; + break; + case 'z': + what |= DUMP_INTERRUPT; + break; + default: + usage(); + /*NOTREACHED*/ + } + strncpy(atd.ad_name, ifname, sizeof (atd.ad_name)); + + argc -= optind; + argv += optind; + if (what == 0) + what = DUMP_BASIC; + + atd.ad_id = HAL_DIAG_REVS; + atd.ad_out_data = (caddr_t) &state.revs; + atd.ad_out_size = sizeof(state.revs); + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + + if (ath_hal_setupregs(&atd, what) == 0) + errx(-1, "no registers are known for this part " + "(devid 0x%x mac %d.%d phy %d)", state.revs.ah_devid, + state.revs.ah_macVersion, state.revs.ah_macRev, + state.revs.ah_phyRev); + + atd.ad_out_size = ath_hal_setupdiagregs((HAL_REGRANGE *) atd.ad_in_data, + atd.ad_in_size / sizeof(HAL_REGRANGE)); + atd.ad_out_data = (caddr_t) malloc(atd.ad_out_size); + if (atd.ad_out_data == NULL) { + fprintf(stderr, "Cannot malloc output buffer, size %u\n", + atd.ad_out_size); + exit(-1); + } + atd.ad_id = HAL_DIAG_REGS | ATH_DIAG_IN | ATH_DIAG_DYN; + if (ioctl(s, SIOCGATHDIAG, &atd) < 0) + err(1, atd.ad_name); + + /* + * Expand register data into global space that can be + * indexed directly by register offset. + */ + dp = (u_int32_t *)atd.ad_out_data; + ep = (u_int32_t *)(atd.ad_out_data + atd.ad_out_size); + while (dp < ep) { + u_int r = dp[0] >> 16; /* start of range */ + u_int e = dp[0] & 0xffff; /* end of range */ + dp++; + /* convert offsets to indices */ + r >>= 2; e >>= 2; + do { + if (dp >= ep) { + fprintf(stderr, "Warning, botched return data;" + "register at offset 0x%x not present\n", + r << 2); + break; + } + state.regdata[r++] = *dp++; + } while (r <= e); + } + + if (what & DUMP_BASIC) + ath_hal_dumpregs(stdout, DUMP_BASIC); + if ((what & DUMP_INTERRUPT) && ath_hal_anyregs(DUMP_INTERRUPT)) { + if (what & DUMP_BASIC) + putchar('\n'); + if (state.show_addrs) + ath_hal_dumpregs(stdout, DUMP_INTERRUPT); + else + ath_hal_dumpint(stdout, what); + } + if ((what & DUMP_QCU) && ath_hal_anyregs(DUMP_QCU)) { + if (what & (DUMP_BASIC|DUMP_INTERRUPT)) + putchar('\n'); + if (state.show_addrs) + ath_hal_dumpregs(stdout, DUMP_QCU); + else + ath_hal_dumpqcu(stdout, what); + } + if ((what & DUMP_DCU) && ath_hal_anyregs(DUMP_DCU)) { + if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU)) + putchar('\n'); + if (state.show_addrs) + ath_hal_dumpregs(stdout, DUMP_DCU); + else + ath_hal_dumpdcu(stdout, what); + } + if (what & DUMP_KEYCACHE) { + if (state.show_addrs) { + if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU|DUMP_DCU)) + putchar('\n'); + ath_hal_dumpregs(stdout, DUMP_KEYCACHE); + } else + ath_hal_dumpkeycache(stdout, 128); + } + if (what & DUMP_BASEBAND) { + if (what &~ DUMP_BASEBAND) + fprintf(stdout, "\n"); + ath_hal_dumpbb(stdout, what); + } + return 0; +} + +static int +regcompar(const void *a, const void *b) +{ + const struct dumpreg *ra = *(const struct dumpreg **)a; + const struct dumpreg *rb = *(const struct dumpreg **)b; + return ra->addr - rb->addr; +} + +void +register_regs(struct dumpreg *chipregs, u_int nchipregs, + int def_srev_min, int def_srev_max, int def_phy_min, int def_phy_max) +{ + const int existing_regs = state.nregs; + int i, j; + + for (i = 0; i < nchipregs; i++) { + struct dumpreg *nr = &chipregs[i]; + if (nr->srevMin == 0) + nr->srevMin = def_srev_min; + if (nr->srevMax == 0) + nr->srevMax = def_srev_max; + if (nr->phyMin == 0) + nr->phyMin = def_phy_min; + if (nr->phyMax == 0) + nr->phyMax = def_phy_max; + for (j = 0; j < existing_regs; j++) { + struct dumpreg *r = state.regs[j]; + /* + * Check if we can just expand the mac+phy + * coverage for the existing entry. + */ + if (nr->addr == r->addr && + (nr->name == r->name || + nr->name != NULL && r->name != NULL && + strcmp(nr->name, r->name) == 0)) { + if (nr->srevMin < r->srevMin && + (r->srevMin <= nr->srevMax && + nr->srevMax+1 <= r->srevMax)) { + r->srevMin = nr->srevMin; + goto skip; + } + if (nr->srevMax > r->srevMax && + (r->srevMin <= nr->srevMin && + nr->srevMin <= r->srevMax)) { + r->srevMax = nr->srevMax; + goto skip; + } + } + if (r->addr > nr->addr) + break; + } + /* + * New item, add to the end, it'll be sorted below. + */ + if (state.nregs == MAXREGS) + errx(-1, "too many registers; bump MAXREGS"); + state.regs[state.nregs++] = nr; + skip: + ; + } + qsort(state.regs, state.nregs, sizeof(struct dumpreg *), regcompar); +} + +void +register_keycache(u_int nslots, + int def_srev_min, int def_srev_max, int def_phy_min, int def_phy_max) +{ +#define SET(r, a) do { \ + r->addr = a; r->type = DUMP_KEYCACHE; r++; \ +} while(0) + struct dumpreg *keyregs, *r; + int i; + + keyregs = (struct dumpreg *) calloc(nslots, 8*sizeof(struct dumpreg)); + if (keyregs == NULL) + errx(-1, "no space to %d keycache slots\n", nslots); + r = keyregs; + for (i = 0; i < nslots; i++) { + SET(r, AR_KEYTABLE_KEY0(i)); + SET(r, AR_KEYTABLE_KEY1(i)); + SET(r, AR_KEYTABLE_KEY2(i)); + SET(r, AR_KEYTABLE_KEY3(i)); + SET(r, AR_KEYTABLE_KEY4(i)); + SET(r, AR_KEYTABLE_TYPE(i)); + SET(r, AR_KEYTABLE_MAC0(i)); + SET(r, AR_KEYTABLE_MAC1(i)); + } + register_regs(keyregs, 8*nslots, + def_srev_min, def_srev_max, def_phy_min, def_phy_max); +#undef SET +} + +void +register_range(u_int brange, u_int erange, int type, + int def_srev_min, int def_srev_max, int def_phy_min, int def_phy_max) +{ + struct dumpreg *bbregs, *r; + int i, nregs; + + nregs = (erange - brange) / sizeof(uint32_t); + bbregs = (struct dumpreg *) calloc(nregs, sizeof(struct dumpreg)); + if (bbregs == NULL) + errx(-1, "no space for %d register slots (type %d)\n", + nregs, type); + r = bbregs; + for (i = 0; i < nregs; i++) { + r->addr = brange + (i<<2); + r->type = type; + r++; + } + register_regs(bbregs, nregs, + def_srev_min, def_srev_max, def_phy_min, def_phy_max); +} + +static __inline +match(const struct dumpreg *dr, const HAL_REVS *revs) +{ + if (!MAC_MATCH(dr, revs->ah_macVersion, revs->ah_macRev)) + return 0; + if ((dr->type & DUMP_BASEBAND) && !PHY_MATCH(dr, revs->ah_phyRev)) + return 0; + return 1; +} + +static int +ath_hal_anyregs(int what) +{ + const HAL_REVS *revs = &state.revs; + int i; + + for (i = 0; i < state.nregs; i++) { + const struct dumpreg *dr = state.regs[i]; + if ((what & dr->type) && match(dr, revs)) + return 1; + } + return 0; +} + +static int +ath_hal_setupregs(struct ath_diag *atd, int what) +{ + const HAL_REVS *revs = &state.revs; + HAL_REGRANGE r; + size_t space = 0; + u_int8_t *cp; + int i, brun, erun; + + brun = erun = -1; + for (i = 0; i < state.nregs; i++) { + const struct dumpreg *dr = state.regs[i]; + if ((what & dr->type) && match(dr, revs)) { + if (erun + 4 != dr->addr) { + if (brun != -1) + space += sizeof(HAL_REGRANGE); + brun = erun = dr->addr; + } else + erun = dr->addr; + } + } + space += sizeof(HAL_REGRANGE); + + atd->ad_in_data = (caddr_t) malloc(space); + if (atd->ad_in_data == NULL) { + fprintf(stderr, "Cannot malloc memory for registers!\n"); + exit(-1); + } + atd->ad_in_size = space; + cp = (u_int8_t *) atd->ad_in_data; + brun = erun = -1; + for (i = 0; i < state.nregs; i++) { + const struct dumpreg *dr = state.regs[i]; + if ((what & dr->type) && match(dr, revs)) { + if (erun + 4 != dr->addr) { + if (brun != -1) { + r.start = brun, r.end = erun; + memcpy(cp, &r, sizeof(r)); + cp += sizeof(r); + } + brun = erun = dr->addr; + } else + erun = dr->addr; + } + } + if (brun != -1) { + r.start = brun, r.end = erun; + memcpy(cp, &r, sizeof(r)); + cp += sizeof(r); + } + return space / sizeof(uint32_t); +} + +static void +ath_hal_dumpregs(FILE *fd, int what) +{ + const HAL_REVS *revs = &state.revs; + const char *sep = ""; + int i, count, itemsperline; + + count = 0; + itemsperline = 4; + if (state.show_names && state.show_addrs) + itemsperline--; + for (i = 0; i < state.nregs; i++) { + const struct dumpreg *dr = state.regs[i]; + if ((what & dr->type) && match(dr, revs)) { + if (state.show_names && dr->name != NULL) { + fprintf(fd, "%s%-8s", sep, dr->name); + if (state.show_addrs) + fprintf(fd, " [%04x]", dr->addr); + } else + fprintf(fd, "%s%04x", sep, dr->addr); + fprintf(fd, " %08x", OS_REG_READ(ah, dr->addr)); + sep = " "; + if ((++count % itemsperline) == 0) + sep = "\n"; + } + } + if (count) + fprintf(fd, "\n"); +} + +static void +ath_hal_dumprange(FILE *fd, u_int a, u_int b) +{ + u_int r; + + for (r = a; r+16 <= b; r += 5*4) + fprintf(fd, + "%04x %08x %04x %08x %04x %08x %04x %08x %04x %08x\n" + , r, OS_REG_READ(ah, r) + , r+4, OS_REG_READ(ah, r+4) + , r+8, OS_REG_READ(ah, r+8) + , r+12, OS_REG_READ(ah, r+12) + , r+16, OS_REG_READ(ah, r+16) + ); + switch (b-r) { + case 16: + fprintf(fd + , "%04x %08x %04x %08x %04x %08x %04x %08x\n" + , r, OS_REG_READ(ah, r) + , r+4, OS_REG_READ(ah, r+4) + , r+8, OS_REG_READ(ah, r+8) + , r+12, OS_REG_READ(ah, r+12) + ); + break; + case 12: + fprintf(fd, "%04x %08x %04x %08x %04x %08x\n" + , r, OS_REG_READ(ah, r) + , r+4, OS_REG_READ(ah, r+4) + , r+8, OS_REG_READ(ah, r+8) + ); + break; + case 8: + fprintf(fd, "%04x %08x %04x %08x\n" + , r, OS_REG_READ(ah, r) + , r+4, OS_REG_READ(ah, r+4) + ); + break; + case 4: + fprintf(fd, "%04x %08x\n" + , r, OS_REG_READ(ah, r) + ); + break; + } +} + +static void +ath_hal_dumpint(FILE *fd, int what) +{ + int i; + + /* Interrupt registers */ + fprintf(fd, "IMR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n" + , OS_REG_READ(ah, AR_IMR) + , OS_REG_READ(ah, AR_IMR_S0) + , OS_REG_READ(ah, AR_IMR_S1) + , OS_REG_READ(ah, AR_IMR_S2) + , OS_REG_READ(ah, AR_IMR_S3) + , OS_REG_READ(ah, AR_IMR_S4) + ); + fprintf(fd, "ISR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n" + , OS_REG_READ(ah, AR_ISR) + , OS_REG_READ(ah, AR_ISR_S0) + , OS_REG_READ(ah, AR_ISR_S1) + , OS_REG_READ(ah, AR_ISR_S2) + , OS_REG_READ(ah, AR_ISR_S3) + , OS_REG_READ(ah, AR_ISR_S4) + ); +} + +static void +ath_hal_dumpqcu(FILE *fd, int what) +{ + int i; + + /* QCU registers */ + fprintf(fd, "%-8s %08x %-8s %08x %-8s %08x\n" + , "Q_TXE", OS_REG_READ(ah, AR_Q_TXE) + , "Q_TXD", OS_REG_READ(ah, AR_Q_TXD) + , "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN) + ); + fprintf(fd, "Q_ONESHOTARM_SC %08x Q_ONESHOTARM_CC %08x\n" + , OS_REG_READ(ah, AR_Q_ONESHOTARM_SC) + , OS_REG_READ(ah, AR_Q_ONESHOTARM_CC) + ); + for (i = 0; i < 10; i++) + fprintf(fd, "Q[%u] TXDP %08x CBR %08x RDYT %08x MISC %08x STS %08x\n" + , i + , OS_REG_READ(ah, AR_QTXDP(i)) + , OS_REG_READ(ah, AR_QCBRCFG(i)) + , OS_REG_READ(ah, AR_QRDYTIMECFG(i)) + , OS_REG_READ(ah, AR_QMISC(i)) + , OS_REG_READ(ah, AR_QSTS(i)) + ); +} + +static void +ath_hal_dumpdcu(FILE *fd, int what) +{ + int i; + + /* DCU registers */ + for (i = 0; i < 10; i++) + fprintf(fd, "D[%u] MASK %08x IFS %08x RTRY %08x CHNT %08x MISC %06x\n" + , i + , OS_REG_READ(ah, AR_DQCUMASK(i)) + , OS_REG_READ(ah, AR_DLCL_IFS(i)) + , OS_REG_READ(ah, AR_DRETRY_LIMIT(i)) + , OS_REG_READ(ah, AR_DCHNTIME(i)) + , OS_REG_READ(ah, AR_DMISC(i)) + ); +} + +static void +ath_hal_dumpbb(FILE *fd, int what) +{ + const HAL_REVS *revs = &state.revs; + int i, brun, erun; + + brun = erun = 0; + for (i = 0; i < state.nregs; i++) { + const struct dumpreg *dr = state.regs[i]; + if (!match(dr, revs)) + continue; + if (dr->type & DUMP_BASEBAND) { + if (brun == 0) { + brun = erun = dr->addr; + } else if (dr->addr == erun + sizeof(uint32_t)) { + erun = dr->addr; + } else { + ath_hal_dumprange(fd, brun, erun); + brun = erun = dr->addr; + } + } else { + if (brun != 0) + ath_hal_dumprange(fd, brun, erun); + brun = erun = 0; + } + } + if (brun != 0) + ath_hal_dumprange(fd, brun, erun); +} + +static u_int +ath_hal_setupdiagregs(const HAL_REGRANGE regs[], u_int nr) +{ + u_int space; + int i; + + space = 0; + for (i = 0; i < nr; i++) { + u_int n = 2 * sizeof(u_int32_t); /* reg range + first */ + if (regs[i].end) { + if (regs[i].end < regs[i].start) { + fprintf(stderr, "%s: bad register range, " + "end 0x%x < start 0x%x\n", + __func__, regs[i].end, regs[i].end); + exit(-1); + } + n += regs[i].end - regs[i].start; + } + space += n; + } + return space; +} + +/* + * Format an Ethernet MAC for printing. + */ +static const char* +ether_sprintf(const u_int8_t *mac) +{ + static char etherbuf[18]; + snprintf(etherbuf, sizeof(etherbuf), "%02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return etherbuf; +} + +#ifndef isclr +#define setbit(a,i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY)) +#define clrbit(a,i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) +#define isset(a,i) ((a)[(i)/NBBY] & (1<<((i)%NBBY))) +#define isclr(a,i) (((a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0) +#endif + +static void +ath_hal_dumpkeycache(FILE *fd, int nkeys) +{ + static const char *keytypenames[] = { + "WEP-40", /* AR_KEYTABLE_TYPE_40 */ + "WEP-104", /* AR_KEYTABLE_TYPE_104 */ + "#2", + "WEP-128", /* AR_KEYTABLE_TYPE_128 */ + "TKIP", /* AR_KEYTABLE_TYPE_TKIP */ + "AES-OCB", /* AR_KEYTABLE_TYPE_AES */ + "AES-CCM", /* AR_KEYTABLE_TYPE_CCM */ + "CLR", /* AR_KEYTABLE_TYPE_CLR */ + }; + int micEnabled = SREV(state.revs.ah_macVersion, state.revs.ah_macRev) < SREV(4,8) ? 0 : + OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_CRPT_MIC_ENABLE; + u_int8_t mac[IEEE80211_ADDR_LEN]; + u_int8_t ismic[128/NBBY]; + int entry; + int first = 1; + + memset(ismic, 0, sizeof(ismic)); + for (entry = 0; entry < nkeys; entry++) { + u_int32_t macLo, macHi, type; + u_int32_t key0, key1, key2, key3, key4; + + macHi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); + if ((macHi & AR_KEYTABLE_VALID) == 0 && isclr(ismic, entry)) + continue; + macLo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); + macHi <<= 1; + if (macLo & (1<<31)) + macHi |= 1; + macLo <<= 1; + mac[4] = macHi & 0xff; + mac[5] = macHi >> 8; + mac[0] = macLo & 0xff; + mac[1] = macLo >> 8; + mac[2] = macLo >> 16; + mac[3] = macLo >> 24; + type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); + if ((type & 7) == AR_KEYTABLE_TYPE_TKIP && micEnabled) + setbit(ismic, entry+64); + key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); + key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); + key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); + key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); + key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); + if (first) { + fprintf(fd, "\n"); + first = 0; + } + fprintf(fd, "KEY[%03u] MAC %s %-7s %02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x\n" + , entry + , ether_sprintf(mac) + , isset(ismic, entry) ? "MIC" : keytypenames[type & 7] + , (key0 >> 0) & 0xff + , (key0 >> 8) & 0xff + , (key0 >> 16) & 0xff + , (key0 >> 24) & 0xff + , (key1 >> 0) & 0xff + , (key1 >> 8) & 0xff + , (key2 >> 0) & 0xff + , (key2 >> 8) & 0xff + , (key2 >> 16) & 0xff + , (key2 >> 24) & 0xff + , (key3 >> 0) & 0xff + , (key3 >> 8) & 0xff + , (key4 >> 0) & 0xff + , (key4 >> 8) & 0xff + , (key4 >> 16) & 0xff + , (key4 >> 24) & 0xff + ); + } +} diff --git a/tools/tools/ath/athregs/dumpregs.h b/tools/tools/ath/athregs/dumpregs.h new file mode 100644 index 000000000000..90fa454ea0a7 --- /dev/null +++ b/tools/tools/ath/athregs/dumpregs.h @@ -0,0 +1,73 @@ +#ifndef _DUMPREGS_ +#define _DUMPREGS_ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#define __constructor __attribute__((constructor)) + +struct dumpreg { + uint32_t addr; + const char *name; + int type; + u_int srevMin, srevMax; + u_int phyMin, phyMax; +}; +#define SREV(v,r) (((v) << 16) | (r)) +#define MAC_MATCH(dr, mv, mr) \ + ((dr)->srevMin <= SREV(mv,mr) && SREV(mv,mr) < (dr)->srevMax) + +#define PHY_MATCH(dr, pr) \ + ((dr)->phyMin <= (pr) && (pr) < (dr)->phyMax) +#define PHYANY 0,0xffff + +enum { + DUMP_BASIC = 0x0001, /* basic/default registers */ + DUMP_KEYCACHE = 0x0002, /* key cache */ + DUMP_BASEBAND = 0x0004, /* baseband */ + DUMP_INTERRUPT = 0x0008, /* interrupt state */ + DUMP_XR = 0x0010, /* XR state */ + DUMP_QCU = 0x0020, /* QCU state */ + DUMP_DCU = 0x0040, /* DCU state */ + + DUMP_PUBLIC = 0x0061, /* public = BASIC+QCU+DCU */ + DUMP_ALL = 0xffff +}; + +void register_regs(struct dumpreg *_regs, u_int _nregs, + int def_srev_min, int def_srev_max, + int def_phy_min, int def_phy_max); +void register_keycache(u_int nslots, + int def_srev_min, int def_srev_max, + int def_phy_min, int def_phy_max); +void register_range(u_int brange, u_int erange, int what, + int def_srev_min, int def_srev_max, + int def_phy_min, int def_phy_max); +#endif /* _DUMPREGS_ */ diff --git a/tools/tools/ath/athregs/dumpregs_5210.c b/tools/tools/ath/athregs/dumpregs_5210.c new file mode 100644 index 000000000000..8d5c86e9b512 --- /dev/null +++ b/tools/tools/ath/athregs/dumpregs_5210.c @@ -0,0 +1,123 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ar5210/ar5210reg.h" + +#include "dumpregs.h" + +#define N(a) (sizeof(a) / sizeof(a[0])) + +static struct dumpreg ar5210regs[] = { + { AR_TXDP0, "TXDP0", DUMP_BASIC }, + { AR_TXDP1, "TXDP1", DUMP_BASIC }, + { AR_CR, "CR", DUMP_BASIC }, + { AR_RXDP, "RXDP", DUMP_BASIC }, + { AR_CFG, "CFG", DUMP_BASIC }, +#if 0 /* read clears pending interrupts */ + { AR_ISR, "ISR", DUMP_INTERRUPT }, +#endif + { AR_IMR, "IMR", DUMP_BASIC }, + { AR_IER, "IER", DUMP_BASIC }, + { AR_BCR, "BCR", DUMP_BASIC }, + { AR_BSR, "BSR", DUMP_BASIC }, + { AR_TXCFG, "TXCFG", DUMP_BASIC }, + { AR_RXCFG, "RXCFG", DUMP_BASIC }, + { AR_MIBC, "MIBC", DUMP_BASIC }, + { AR_TOPS, "TOPS", DUMP_BASIC }, + { AR_RXNOFRM, "RXNOFR", DUMP_BASIC }, + { AR_TXNOFRM, "TXNOFR", DUMP_BASIC }, + { AR_RPGTO, "RPGTO", DUMP_BASIC }, + { AR_RFCNT, "RFCNT", DUMP_BASIC }, + { AR_MISC, "MISC", DUMP_BASIC }, + { AR_RC, "RC", DUMP_BASIC }, + { AR_SCR, "SCR", DUMP_BASIC }, + { AR_INTPEND, "INTPEND", DUMP_BASIC }, + { AR_SFR, "SFR", DUMP_BASIC }, + { AR_PCICFG, "PCICFG", DUMP_BASIC }, + { AR_GPIOCR, "GPIOCR", DUMP_BASIC }, +#if 0 + { AR_GPIODO, "GPIODO", DUMP_BASIC }, + { AR_GPIODI, "GPIODI", DUMP_BASIC }, +#endif + { AR_SREV, "SREV", DUMP_BASIC }, + { AR_STA_ID0, "STA_ID0", DUMP_BASIC }, + { AR_STA_ID1, "STA_ID1", DUMP_BASIC }, + { AR_BSS_ID0, "BSS_ID0", DUMP_BASIC }, + { AR_BSS_ID1, "BSS_ID1", DUMP_BASIC }, + { AR_SLOT_TIME, "SLOTTIME", DUMP_BASIC }, + { AR_TIME_OUT, "TIME_OUT", DUMP_BASIC }, + { AR_RSSI_THR, "RSSI_THR", DUMP_BASIC }, + { AR_RETRY_LMT, "RETRY_LM", DUMP_BASIC }, + { AR_USEC, "USEC", DUMP_BASIC }, + { AR_BEACON, "BEACON", DUMP_BASIC }, + { AR_CFP_PERIOD, "CFP_PER", DUMP_BASIC }, + { AR_TIMER0, "TIMER0", DUMP_BASIC }, + { AR_TIMER1, "TIMER1", DUMP_BASIC }, + { AR_TIMER2, "TIMER2", DUMP_BASIC }, + { AR_TIMER3, "TIMER3", DUMP_BASIC }, + { AR_IFS0, "IFS0", DUMP_BASIC }, + { AR_IFS1, "IFS1" , DUMP_BASIC }, + { AR_CFP_DUR, "CFP_DUR", DUMP_BASIC }, + { AR_RX_FILTER, "RXFILTER", DUMP_BASIC }, + { AR_MCAST_FIL0, "MCAST_0", DUMP_BASIC }, + { AR_MCAST_FIL1, "MCAST_1", DUMP_BASIC }, + { AR_TX_MASK0, "TX_MASK0", DUMP_BASIC }, + { AR_TX_MASK1, "TX_MASK1", DUMP_BASIC }, +#if 0 + { AR_CLR_TMASK, "CLR_TMASK", DUMP_BASIC }, +#endif + { AR_TRIG_LEV, "TRIG_LEV", DUMP_BASIC }, + { AR_DIAG_SW, "DIAG_SW", DUMP_BASIC }, + { AR_TSF_L32, "TSF_L32", DUMP_BASIC }, + { AR_TSF_U32, "TSF_U32", DUMP_BASIC }, + { AR_LAST_TSTP, "LAST_TST", DUMP_BASIC }, + { AR_RETRY_CNT, "RETRYCNT", DUMP_BASIC }, + { AR_BACKOFF, "BACKOFF", DUMP_BASIC }, + { AR_NAV, "NAV", DUMP_BASIC }, + { AR_RTS_OK, "RTS_OK", DUMP_BASIC }, + { AR_RTS_FAIL, "RTS_FAIL", DUMP_BASIC }, + { AR_ACK_FAIL, "ACK_FAIL", DUMP_BASIC }, + { AR_FCS_FAIL, "FCS_FAIL", DUMP_BASIC }, + { AR_BEACON_CNT, "BEAC_CNT", DUMP_BASIC }, +}; + +static __constructor void +ar5210_ctor(void) +{ +#define MAC5210 SREV(1,0), SREV(2,0) + register_regs(ar5210regs, N(ar5210regs), MAC5210, PHYANY); + register_keycache(64, MAC5210, PHYANY); + + register_range(0x9800, 0x9840, DUMP_BASEBAND, MAC5210, PHYANY); +} diff --git a/tools/tools/ath/athregs/dumpregs_5211.c b/tools/tools/ath/athregs/dumpregs_5211.c new file mode 100644 index 000000000000..71d778966c96 --- /dev/null +++ b/tools/tools/ath/athregs/dumpregs_5211.c @@ -0,0 +1,281 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ar5211/ar5211reg.h" + +#include "dumpregs.h" + +#define N(a) (sizeof(a) / sizeof(a[0])) + +static struct dumpreg ar5211regs[] = { + { AR_CR, "CR", DUMP_BASIC }, + { AR_RXDP, "RXDP", DUMP_BASIC }, + { AR_CFG, "CFG", DUMP_BASIC }, + { AR_IER, "IER", DUMP_BASIC }, + { AR_RTSD0, "RTSD0", DUMP_BASIC }, + { AR_RTSD1, "RTSD1", DUMP_BASIC }, + { AR_TXCFG, "TXCFG", DUMP_BASIC }, + { AR_RXCFG, "RXCFG", DUMP_BASIC }, + { AR5211_JUMBO_LAST,"JLAST", DUMP_BASIC }, + { AR_MIBC, "MIBC", DUMP_BASIC }, + { AR_TOPS, "TOPS", DUMP_BASIC }, + { AR_RXNPTO, "RXNPTO", DUMP_BASIC }, + { AR_TXNPTO, "TXNPTO", DUMP_BASIC }, + { AR_RFGTO, "RFGTO", DUMP_BASIC }, + { AR_RFCNT, "RFCNT", DUMP_BASIC }, + { AR_MACMISC, "MISC", DUMP_BASIC }, + + { AR_ISR, "ISR", DUMP_INTERRUPT }, + { AR_ISR_S0, "ISR_S0", DUMP_INTERRUPT }, + { AR_ISR_S1, "ISR_S1", DUMP_INTERRUPT }, + { AR_ISR_S2, "ISR_S2", DUMP_INTERRUPT }, + { AR_ISR_S3, "ISR_S3", DUMP_INTERRUPT }, + { AR_ISR_S4, "ISR_S4", DUMP_INTERRUPT }, + { AR_IMR, "IMR", DUMP_INTERRUPT }, + { AR_IMR_S0, "IMR_S0", DUMP_INTERRUPT }, + { AR_IMR_S1, "IMR_S1", DUMP_INTERRUPT }, + { AR_IMR_S2, "IMR_S2", DUMP_INTERRUPT }, + { AR_IMR_S3, "IMR_S3", DUMP_INTERRUPT }, + { AR_IMR_S4, "IMR_S4", DUMP_INTERRUPT }, +#if 0 + /* NB: don't read the RAC so we don't affect operation */ + { AR_ISR_RAC, "ISR_RAC", DUMP_INTERRUPT }, +#endif + { AR_ISR_S0_S, "ISR_S0_S", DUMP_INTERRUPT }, + { AR_ISR_S1_S, "ISR_S1_S", DUMP_INTERRUPT }, + { AR_ISR_S2_S, "ISR_S2_S", DUMP_INTERRUPT }, + { AR_ISR_S3_S, "ISR_S3_S", DUMP_INTERRUPT }, + { AR_ISR_S4_S, "ISR_S4_S", DUMP_INTERRUPT }, + + { AR_Q0_TXDP, "Q0_TXDP", DUMP_QCU }, + { AR_Q1_TXDP, "Q1_TXDP", DUMP_QCU }, + { AR_Q2_TXDP, "Q2_TXDP", DUMP_QCU }, + { AR_Q3_TXDP, "Q3_TXDP", DUMP_QCU }, + { AR_Q4_TXDP, "Q4_TXDP", DUMP_QCU }, + { AR_Q5_TXDP, "Q5_TXDP", DUMP_QCU }, + { AR_Q6_TXDP, "Q6_TXDP", DUMP_QCU }, + { AR_Q7_TXDP, "Q7_TXDP", DUMP_QCU }, + { AR_Q8_TXDP, "Q8_TXDP", DUMP_QCU }, + { AR_Q9_TXDP, "Q9_TXDP", DUMP_QCU }, + + { AR_Q_TXE, "Q_TXE", DUMP_QCU }, + { AR_Q_TXD, "Q_TXD", DUMP_QCU }, + + { AR_Q0_CBRCFG, "Q0_CBR", DUMP_QCU }, + { AR_Q1_CBRCFG, "Q1_CBR", DUMP_QCU }, + { AR_Q2_CBRCFG, "Q2_CBR", DUMP_QCU }, + { AR_Q3_CBRCFG, "Q3_CBR", DUMP_QCU }, + { AR_Q4_CBRCFG, "Q4_CBR", DUMP_QCU }, + { AR_Q5_CBRCFG, "Q5_CBR", DUMP_QCU }, + { AR_Q6_CBRCFG, "Q6_CBR", DUMP_QCU }, + { AR_Q7_CBRCFG, "Q7_CBR", DUMP_QCU }, + { AR_Q8_CBRCFG, "Q8_CBR", DUMP_QCU }, + { AR_Q9_CBRCFG, "Q9_CBR", DUMP_QCU }, + + { AR_Q0_RDYTIMECFG, "Q0_RDYT", DUMP_QCU }, + { AR_Q1_RDYTIMECFG, "Q1_RDYT", DUMP_QCU }, + { AR_Q2_RDYTIMECFG, "Q2_RDYT", DUMP_QCU }, + { AR_Q3_RDYTIMECFG, "Q3_RDYT", DUMP_QCU }, + { AR_Q4_RDYTIMECFG, "Q4_RDYT", DUMP_QCU }, + { AR_Q5_RDYTIMECFG, "Q5_RDYT", DUMP_QCU }, + { AR_Q6_RDYTIMECFG, "Q6_RDYT", DUMP_QCU }, + { AR_Q7_RDYTIMECFG, "Q7_RDYT", DUMP_QCU }, + { AR_Q8_RDYTIMECFG, "Q8_RDYT", DUMP_QCU }, + { AR_Q9_RDYTIMECFG, "Q9_RDYT", DUMP_QCU }, + + { AR_Q_ONESHOTARM_SC,"Q_ONESHOTARM_SC", DUMP_QCU }, + { AR_Q_ONESHOTARM_CC,"Q_ONESHOTARM_CC", DUMP_QCU }, + + { AR_Q0_MISC, "Q0_MISC", DUMP_QCU }, + { AR_Q1_MISC, "Q1_MISC", DUMP_QCU }, + { AR_Q2_MISC, "Q2_MISC", DUMP_QCU }, + { AR_Q3_MISC, "Q3_MISC", DUMP_QCU }, + { AR_Q4_MISC, "Q4_MISC", DUMP_QCU }, + { AR_Q5_MISC, "Q5_MISC", DUMP_QCU }, + { AR_Q6_MISC, "Q6_MISC", DUMP_QCU }, + { AR_Q7_MISC, "Q7_MISC", DUMP_QCU }, + { AR_Q8_MISC, "Q8_MISC", DUMP_QCU }, + { AR_Q9_MISC, "Q9_MISC", DUMP_QCU }, + + { AR_Q0_STS, "Q0_STS", DUMP_QCU }, + { AR_Q1_STS, "Q1_STS", DUMP_QCU }, + { AR_Q2_STS, "Q2_STS", DUMP_QCU }, + { AR_Q3_STS, "Q3_STS", DUMP_QCU }, + { AR_Q4_STS, "Q4_STS", DUMP_QCU }, + { AR_Q5_STS, "Q5_STS", DUMP_QCU }, + { AR_Q6_STS, "Q6_STS", DUMP_QCU }, + { AR_Q7_STS, "Q7_STS", DUMP_QCU }, + { AR_Q8_STS, "Q8_STS", DUMP_QCU }, + { AR_Q9_STS, "Q9_STS", DUMP_QCU }, + + { AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD", DUMP_QCU }, + + { AR_D0_QCUMASK, "D0_MASK", DUMP_DCU }, + { AR_D1_QCUMASK, "D1_MASK", DUMP_DCU }, + { AR_D2_QCUMASK, "D2_MASK", DUMP_DCU }, + { AR_D3_QCUMASK, "D3_MASK", DUMP_DCU }, + { AR_D4_QCUMASK, "D4_MASK", DUMP_DCU }, + { AR_D5_QCUMASK, "D5_MASK", DUMP_DCU }, + { AR_D6_QCUMASK, "D6_MASK", DUMP_DCU }, + { AR_D7_QCUMASK, "D7_MASK", DUMP_DCU }, + { AR_D8_QCUMASK, "D8_MASK", DUMP_DCU }, + { AR_D9_QCUMASK, "D9_MASK", DUMP_DCU }, + + { AR_D0_LCL_IFS, "D0_IFS", DUMP_DCU }, + { AR_D1_LCL_IFS, "D1_IFS", DUMP_DCU }, + { AR_D2_LCL_IFS, "D2_IFS", DUMP_DCU }, + { AR_D3_LCL_IFS, "D3_IFS", DUMP_DCU }, + { AR_D4_LCL_IFS, "D4_IFS", DUMP_DCU }, + { AR_D5_LCL_IFS, "D5_IFS", DUMP_DCU }, + { AR_D6_LCL_IFS, "D6_IFS", DUMP_DCU }, + { AR_D7_LCL_IFS, "D7_IFS", DUMP_DCU }, + { AR_D8_LCL_IFS, "D8_IFS", DUMP_DCU }, + { AR_D9_LCL_IFS, "D9_IFS", DUMP_DCU }, + + { AR_D0_RETRY_LIMIT,"D0_RTRY", DUMP_DCU }, + { AR_D1_RETRY_LIMIT,"D1_RTRY", DUMP_DCU }, + { AR_D2_RETRY_LIMIT,"D2_RTRY", DUMP_DCU }, + { AR_D3_RETRY_LIMIT,"D3_RTRY", DUMP_DCU }, + { AR_D4_RETRY_LIMIT,"D4_RTRY", DUMP_DCU }, + { AR_D5_RETRY_LIMIT,"D5_RTRY", DUMP_DCU }, + { AR_D6_RETRY_LIMIT,"D6_RTRY", DUMP_DCU }, + { AR_D7_RETRY_LIMIT,"D7_RTRY", DUMP_DCU }, + { AR_D8_RETRY_LIMIT,"D8_RTRY", DUMP_DCU }, + { AR_D9_RETRY_LIMIT,"D9_RTRY", DUMP_DCU }, + + { AR_D0_CHNTIME, "D0_CHNT", DUMP_DCU }, + { AR_D1_CHNTIME, "D1_CHNT", DUMP_DCU }, + { AR_D2_CHNTIME, "D2_CHNT", DUMP_DCU }, + { AR_D3_CHNTIME, "D3_CHNT", DUMP_DCU }, + { AR_D4_CHNTIME, "D4_CHNT", DUMP_DCU }, + { AR_D5_CHNTIME, "D5_CHNT", DUMP_DCU }, + { AR_D6_CHNTIME, "D6_CHNT", DUMP_DCU }, + { AR_D7_CHNTIME, "D7_CHNT", DUMP_DCU }, + { AR_D8_CHNTIME, "D8_CHNT", DUMP_DCU }, + { AR_D9_CHNTIME, "D9_CHNT", DUMP_DCU }, + + { AR_D0_MISC, "D0_MISC", DUMP_DCU }, + { AR_D1_MISC, "D1_MISC", DUMP_DCU }, + { AR_D2_MISC, "D2_MISC", DUMP_DCU }, + { AR_D3_MISC, "D3_MISC", DUMP_DCU }, + { AR_D4_MISC, "D4_MISC", DUMP_DCU }, + { AR_D5_MISC, "D5_MISC", DUMP_DCU }, + { AR_D6_MISC, "D6_MISC", DUMP_DCU }, + { AR_D7_MISC, "D7_MISC", DUMP_DCU }, + { AR_D8_MISC, "D8_MISC", DUMP_DCU }, + { AR_D9_MISC, "D9_MISC", DUMP_DCU }, + + { AR_D0_SEQNUM, "D0_SEQ", DUMP_DCU }, + { AR_D1_SEQNUM, "D1_SEQ", DUMP_DCU }, + { AR_D2_SEQNUM, "D2_SEQ", DUMP_DCU }, + { AR_D3_SEQNUM, "D3_SEQ", DUMP_DCU }, + { AR_D4_SEQNUM, "D4_SEQ", DUMP_DCU }, + { AR_D5_SEQNUM, "D5_SEQ", DUMP_DCU }, + { AR_D6_SEQNUM, "D6_SEQ", DUMP_DCU }, + { AR_D7_SEQNUM, "D7_SEQ", DUMP_DCU }, + { AR_D8_SEQNUM, "D8_SEQ", DUMP_DCU }, + { AR_D9_SEQNUM, "D9_SEQ", DUMP_DCU }, + + { AR_D_GBL_IFS_SIFS,"D_SIFS", DUMP_BASIC }, + { AR_D_GBL_IFS_SLOT,"D_SLOT", DUMP_BASIC }, + { AR_D_GBL_IFS_EIFS,"D_EIFS", DUMP_BASIC }, + { AR_D_GBL_IFS_MISC,"D_MISC", DUMP_BASIC }, + { AR_D_FPCTL, "D_FPCTL", DUMP_BASIC }, + { AR_D_TXPSE, "D_TXPSE", DUMP_BASIC }, +#if 0 + { AR_D_TXBLK_CMD, "D_CMD", DUMP_BASIC }, + { AR_D_TXBLK_DATA, "D_DATA", DUMP_BASIC }, + { AR_D_TXBLK_CLR, "D_CLR", DUMP_BASIC }, + { AR_D_TXBLK_SET, "D_SET", DUMP_BASIC }, +#endif + { AR_RC, "RC", DUMP_BASIC }, + { AR_SCR, "SCR", DUMP_BASIC }, + { AR_INTPEND, "INTPEND", DUMP_BASIC }, + { AR_SFR, "SFR", DUMP_BASIC }, + { AR_PCICFG, "PCICFG", DUMP_BASIC }, + { AR_GPIOCR, "GPIOCR", DUMP_BASIC }, + { AR_GPIODO, "GPIODO", DUMP_BASIC }, + { AR_GPIODI, "GPIODI", DUMP_BASIC }, + { AR_SREV, "SREV", DUMP_BASIC }, +#if 0 + { AR_EEPROM_ADDR, "EEADDR", DUMP_BASIC }, + { AR_EEPROM_DATA, "EEDATA", DUMP_BASIC }, + { AR_EEPROM_CMD, "EECMD", DUMP_BASIC }, + { AR_EEPROM_STS, "EESTS", DUMP_BASIC }, + { AR_EEPROM_CFG, "EECFG", DUMP_BASIC }, +#endif + { AR_STA_ID0, "STA_ID0", DUMP_BASIC }, + { AR_STA_ID1, "STA_ID1", DUMP_BASIC }, + { AR_BSS_ID0, "BSS_ID0", DUMP_BASIC }, + { AR_BSS_ID1, "BSS_ID1", DUMP_BASIC }, + { AR_SLOT_TIME, "SLOTTIME", DUMP_BASIC }, + { AR_TIME_OUT, "TIME_OUT", DUMP_BASIC }, + { AR_RSSI_THR, "RSSI_THR", DUMP_BASIC }, + { AR_USEC, "USEC", DUMP_BASIC }, + { AR_BEACON, "BEACON", DUMP_BASIC }, + { AR_CFP_PERIOD, "CFP_PER", DUMP_BASIC }, + { AR_TIMER0, "TIMER0", DUMP_BASIC }, + { AR_TIMER1, "TIMER1", DUMP_BASIC }, + { AR_TIMER2, "TIMER2", DUMP_BASIC }, + { AR_TIMER3, "TIMER3", DUMP_BASIC }, + { AR_CFP_DUR, "CFP_DUR", DUMP_BASIC }, + { AR_RX_FILTER, "RXFILTER", DUMP_BASIC }, + { AR_MCAST_FIL0, "MCAST_0", DUMP_BASIC }, + { AR_MCAST_FIL1, "MCAST_1", DUMP_BASIC }, + { AR_DIAG_SW, "DIAG_SW", DUMP_BASIC }, + { AR_TSF_L32, "TSF_L32", DUMP_BASIC }, + { AR_TSF_U32, "TSF_U32", DUMP_BASIC }, + { AR_TST_ADDAC, "TST_ADAC", DUMP_BASIC }, + { AR_DEF_ANTENNA, "DEF_ANT", DUMP_BASIC }, + + { AR_LAST_TSTP, "LAST_TST", DUMP_BASIC }, + { AR_NAV, "NAV", DUMP_BASIC }, + { AR_RTS_OK, "RTS_OK", DUMP_BASIC }, + { AR_RTS_FAIL, "RTS_FAIL", DUMP_BASIC }, + { AR_ACK_FAIL, "ACK_FAIL", DUMP_BASIC }, + { AR_FCS_FAIL, "FCS_FAIL", DUMP_BASIC }, + { AR_BEACON_CNT, "BEAC_CNT", DUMP_BASIC }, +}; + +static __constructor void +ar5211_ctor(void) +{ +#define MAC5211 SREV(2,0), SREV(4,5) + register_regs(ar5211regs, N(ar5211regs), MAC5211, PHYANY); + register_keycache(128, MAC5211, PHYANY); + + register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5211, PHYANY); + register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5211, PHYANY); + register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5211, PHYANY); +} diff --git a/tools/tools/ath/athregs/dumpregs_5212.c b/tools/tools/ath/athregs/dumpregs_5212.c new file mode 100644 index 000000000000..5c90d1f9207a --- /dev/null +++ b/tools/tools/ath/athregs/dumpregs_5212.c @@ -0,0 +1,335 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ar5212/ar5212reg.h" +#include "ar5212/ar5212phy.h" + +#include "dumpregs.h" + +#define N(a) (sizeof(a) / sizeof(a[0])) + +#define MAC5212 SREV(4,5), SREV(16,0) +#define MAC5213 SREV(5,9), SREV(16,0) + +static struct dumpreg ar5212regs[] = { + { AR_CR, "CR", DUMP_BASIC }, + { AR_RXDP, "RXDP", DUMP_BASIC }, + { AR_CFG, "CFG", DUMP_BASIC }, + { AR_IER, "IER", DUMP_BASIC }, + { AR_TXCFG, "TXCFG", DUMP_BASIC }, + { AR_RXCFG, "RXCFG", DUMP_BASIC }, + { AR_MIBC, "MIBC", DUMP_BASIC }, + { AR_TOPS, "TOPS", DUMP_BASIC }, + { AR_RXNPTO, "RXNPTO", DUMP_BASIC }, + { AR_TXNPTO, "TXNPTO", DUMP_BASIC }, + { AR_RPGTO, "RPGTO", DUMP_BASIC }, + { AR_RPCNT, "RPCNT", DUMP_BASIC }, + { AR_MACMISC, "MACMISC", DUMP_BASIC }, + { AR_SPC_0, "SPC_0", DUMP_BASIC }, + { AR_SPC_1, "SPC_1", DUMP_BASIC }, + + { AR_ISR, "ISR", DUMP_INTERRUPT }, + { AR_ISR_S0, "ISR_S0", DUMP_INTERRUPT }, + { AR_ISR_S1, "ISR_S1", DUMP_INTERRUPT }, + { AR_ISR_S2, "ISR_S2", DUMP_INTERRUPT }, + { AR_ISR_S3, "ISR_S3", DUMP_INTERRUPT }, + { AR_ISR_S4, "ISR_S4", DUMP_INTERRUPT }, + { AR_IMR, "IMR", DUMP_INTERRUPT }, + { AR_IMR_S0, "IMR_S0", DUMP_INTERRUPT }, + { AR_IMR_S1, "IMR_S1", DUMP_INTERRUPT }, + { AR_IMR_S2, "IMR_S2", DUMP_INTERRUPT }, + { AR_IMR_S3, "IMR_S3", DUMP_INTERRUPT }, + { AR_IMR_S4, "IMR_S4", DUMP_INTERRUPT }, +#if 0 + /* NB: don't read the RAC so we don't affect operation */ + { AR_ISR_RAC, "ISR_RAC", DUMP_INTERRUPT }, +#endif + { AR_ISR_S0_S, "ISR_S0_S", DUMP_INTERRUPT }, + { AR_ISR_S1_S, "ISR_S1_S", DUMP_INTERRUPT }, + { AR_ISR_S2_S, "ISR_S2_S", DUMP_INTERRUPT }, + { AR_ISR_S3_S, "ISR_S3_S", DUMP_INTERRUPT }, + { AR_ISR_S4_S, "ISR_S4_S", DUMP_INTERRUPT }, + + { AR_DMADBG_0, "DMADBG0", DUMP_BASIC }, + { AR_DMADBG_1, "DMADBG1", DUMP_BASIC }, + { AR_DMADBG_2, "DMADBG2", DUMP_BASIC }, + { AR_DMADBG_3, "DMADBG3", DUMP_BASIC }, + { AR_DMADBG_4, "DMADBG4", DUMP_BASIC }, + { AR_DMADBG_5, "DMADBG5", DUMP_BASIC }, + { AR_DMADBG_6, "DMADBG6", DUMP_BASIC }, + { AR_DMADBG_7, "DMADBG7", DUMP_BASIC }, + + { AR_DCM_A, "DCM_A", DUMP_BASIC }, + { AR_DCM_D, "DCM_D", DUMP_BASIC }, + { AR_DCCFG, "DCCFG", DUMP_BASIC }, + { AR_CCFG, "CCFG", DUMP_BASIC }, + { AR_CCUCFG, "CCUCFG", DUMP_BASIC }, + { AR_CPC_0, "CPC0", DUMP_BASIC }, + { AR_CPC_1, "CPC1", DUMP_BASIC }, + { AR_CPC_2, "CPC2", DUMP_BASIC }, + { AR_CPC_3, "CPC3", DUMP_BASIC }, + { AR_CPCOVF, "CPCOVF", DUMP_BASIC }, + + { AR_Q0_TXDP, "Q0_TXDP", DUMP_QCU }, + { AR_Q1_TXDP, "Q1_TXDP", DUMP_QCU }, + { AR_Q2_TXDP, "Q2_TXDP", DUMP_QCU }, + { AR_Q3_TXDP, "Q3_TXDP", DUMP_QCU }, + { AR_Q4_TXDP, "Q4_TXDP", DUMP_QCU }, + { AR_Q5_TXDP, "Q5_TXDP", DUMP_QCU }, + { AR_Q6_TXDP, "Q6_TXDP", DUMP_QCU }, + { AR_Q7_TXDP, "Q7_TXDP", DUMP_QCU }, + { AR_Q8_TXDP, "Q8_TXDP", DUMP_QCU }, + { AR_Q9_TXDP, "Q9_TXDP", DUMP_QCU }, + + { AR_Q_TXE, "Q_TXE", DUMP_QCU }, + { AR_Q_TXD, "Q_TXD", DUMP_QCU }, + + { AR_Q0_CBRCFG, "Q0_CBR", DUMP_QCU }, + { AR_Q1_CBRCFG, "Q1_CBR", DUMP_QCU }, + { AR_Q2_CBRCFG, "Q2_CBR", DUMP_QCU }, + { AR_Q3_CBRCFG, "Q3_CBR", DUMP_QCU }, + { AR_Q4_CBRCFG, "Q4_CBR", DUMP_QCU }, + { AR_Q5_CBRCFG, "Q5_CBR", DUMP_QCU }, + { AR_Q6_CBRCFG, "Q6_CBR", DUMP_QCU }, + { AR_Q7_CBRCFG, "Q7_CBR", DUMP_QCU }, + { AR_Q8_CBRCFG, "Q8_CBR", DUMP_QCU }, + { AR_Q9_CBRCFG, "Q9_CBR", DUMP_QCU }, + + { AR_Q0_RDYTIMECFG, "Q0_RDYT", DUMP_QCU }, + { AR_Q1_RDYTIMECFG, "Q1_RDYT", DUMP_QCU }, + { AR_Q2_RDYTIMECFG, "Q2_RDYT", DUMP_QCU }, + { AR_Q3_RDYTIMECFG, "Q3_RDYT", DUMP_QCU }, + { AR_Q4_RDYTIMECFG, "Q4_RDYT", DUMP_QCU }, + { AR_Q5_RDYTIMECFG, "Q5_RDYT", DUMP_QCU }, + { AR_Q6_RDYTIMECFG, "Q6_RDYT", DUMP_QCU }, + { AR_Q7_RDYTIMECFG, "Q7_RDYT", DUMP_QCU }, + { AR_Q8_RDYTIMECFG, "Q8_RDYT", DUMP_QCU }, + { AR_Q9_RDYTIMECFG, "Q9_RDYT", DUMP_QCU }, + + { AR_Q_ONESHOTARM_SC,"Q_ONESHOTARM_SC", DUMP_QCU }, + { AR_Q_ONESHOTARM_CC,"Q_ONESHOTARM_CC", DUMP_QCU }, + + { AR_Q0_MISC, "Q0_MISC", DUMP_QCU }, + { AR_Q1_MISC, "Q1_MISC", DUMP_QCU }, + { AR_Q2_MISC, "Q2_MISC", DUMP_QCU }, + { AR_Q3_MISC, "Q3_MISC", DUMP_QCU }, + { AR_Q4_MISC, "Q4_MISC", DUMP_QCU }, + { AR_Q5_MISC, "Q5_MISC", DUMP_QCU }, + { AR_Q6_MISC, "Q6_MISC", DUMP_QCU }, + { AR_Q7_MISC, "Q7_MISC", DUMP_QCU }, + { AR_Q8_MISC, "Q8_MISC", DUMP_QCU }, + { AR_Q9_MISC, "Q9_MISC", DUMP_QCU }, + + { AR_Q0_STS, "Q0_STS", DUMP_QCU }, + { AR_Q1_STS, "Q1_STS", DUMP_QCU }, + { AR_Q2_STS, "Q2_STS", DUMP_QCU }, + { AR_Q3_STS, "Q3_STS", DUMP_QCU }, + { AR_Q4_STS, "Q4_STS", DUMP_QCU }, + { AR_Q5_STS, "Q5_STS", DUMP_QCU }, + { AR_Q6_STS, "Q6_STS", DUMP_QCU }, + { AR_Q7_STS, "Q7_STS", DUMP_QCU }, + { AR_Q8_STS, "Q8_STS", DUMP_QCU }, + { AR_Q9_STS, "Q9_STS", DUMP_QCU }, + + { AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD", DUMP_QCU }, + + { AR_Q_CBBS, "Q_CBBS", DUMP_QCU }, + { AR_Q_CBBA, "Q_CBBA", DUMP_QCU }, + { AR_Q_CBC, "Q_CBC", DUMP_QCU }, + + { AR_D0_QCUMASK, "D0_MASK", DUMP_DCU }, + { AR_D1_QCUMASK, "D1_MASK", DUMP_DCU }, + { AR_D2_QCUMASK, "D2_MASK", DUMP_DCU }, + { AR_D3_QCUMASK, "D3_MASK", DUMP_DCU }, + { AR_D4_QCUMASK, "D4_MASK", DUMP_DCU }, + { AR_D5_QCUMASK, "D5_MASK", DUMP_DCU }, + { AR_D6_QCUMASK, "D6_MASK", DUMP_DCU }, + { AR_D7_QCUMASK, "D7_MASK", DUMP_DCU }, + { AR_D8_QCUMASK, "D8_MASK", DUMP_DCU }, + { AR_D9_QCUMASK, "D9_MASK", DUMP_DCU }, + + { AR_D0_LCL_IFS, "D0_IFS", DUMP_DCU }, + { AR_D1_LCL_IFS, "D1_IFS", DUMP_DCU }, + { AR_D2_LCL_IFS, "D2_IFS", DUMP_DCU }, + { AR_D3_LCL_IFS, "D3_IFS", DUMP_DCU }, + { AR_D4_LCL_IFS, "D4_IFS", DUMP_DCU }, + { AR_D5_LCL_IFS, "D5_IFS", DUMP_DCU }, + { AR_D6_LCL_IFS, "D6_IFS", DUMP_DCU }, + { AR_D7_LCL_IFS, "D7_IFS", DUMP_DCU }, + { AR_D8_LCL_IFS, "D8_IFS", DUMP_DCU }, + { AR_D9_LCL_IFS, "D9_IFS", DUMP_DCU }, + + { AR_D0_RETRY_LIMIT,"D0_RTRY", DUMP_DCU }, + { AR_D1_RETRY_LIMIT,"D1_RTRY", DUMP_DCU }, + { AR_D2_RETRY_LIMIT,"D2_RTRY", DUMP_DCU }, + { AR_D3_RETRY_LIMIT,"D3_RTRY", DUMP_DCU }, + { AR_D4_RETRY_LIMIT,"D4_RTRY", DUMP_DCU }, + { AR_D5_RETRY_LIMIT,"D5_RTRY", DUMP_DCU }, + { AR_D6_RETRY_LIMIT,"D6_RTRY", DUMP_DCU }, + { AR_D7_RETRY_LIMIT,"D7_RTRY", DUMP_DCU }, + { AR_D8_RETRY_LIMIT,"D8_RTRY", DUMP_DCU }, + { AR_D9_RETRY_LIMIT,"D9_RTRY", DUMP_DCU }, + + { AR_D0_CHNTIME, "D0_CHNT", DUMP_DCU }, + { AR_D1_CHNTIME, "D1_CHNT", DUMP_DCU }, + { AR_D2_CHNTIME, "D2_CHNT", DUMP_DCU }, + { AR_D3_CHNTIME, "D3_CHNT", DUMP_DCU }, + { AR_D4_CHNTIME, "D4_CHNT", DUMP_DCU }, + { AR_D5_CHNTIME, "D5_CHNT", DUMP_DCU }, + { AR_D6_CHNTIME, "D6_CHNT", DUMP_DCU }, + { AR_D7_CHNTIME, "D7_CHNT", DUMP_DCU }, + { AR_D8_CHNTIME, "D8_CHNT", DUMP_DCU }, + { AR_D9_CHNTIME, "D9_CHNT", DUMP_DCU }, + + { AR_D0_MISC, "D0_MISC", DUMP_DCU }, + { AR_D1_MISC, "D1_MISC", DUMP_DCU }, + { AR_D2_MISC, "D2_MISC", DUMP_DCU }, + { AR_D3_MISC, "D3_MISC", DUMP_DCU }, + { AR_D4_MISC, "D4_MISC", DUMP_DCU }, + { AR_D5_MISC, "D5_MISC", DUMP_DCU }, + { AR_D6_MISC, "D6_MISC", DUMP_DCU }, + { AR_D7_MISC, "D7_MISC", DUMP_DCU }, + { AR_D8_MISC, "D8_MISC", DUMP_DCU }, + { AR_D9_MISC, "D9_MISC", DUMP_DCU }, + + { AR_D_SEQNUM, "D_SEQ", DUMP_BASIC | DUMP_DCU }, + { AR_D_GBL_IFS_SIFS,"D_SIFS", DUMP_BASIC }, + { AR_D_GBL_IFS_SLOT,"D_SLOT", DUMP_BASIC }, + { AR_D_GBL_IFS_EIFS,"D_EIFS", DUMP_BASIC }, + { AR_D_GBL_IFS_MISC,"D_MISC", DUMP_BASIC }, + { AR_D_FPCTL, "D_FPCTL", DUMP_BASIC }, + { AR_D_TXPSE, "D_TXPSE", DUMP_BASIC }, +#if 0 + { AR_D_TXBLK_CMD, "D_CMD", DUMP_BASIC }, + { AR_D_TXBLK_DATA, "D_DATA", DUMP_BASIC }, + { AR_D_TXBLK_CLR, "D_CLR", DUMP_BASIC }, + { AR_D_TXBLK_SET, "D_SET", DUMP_BASIC }, +#endif + { AR_RC, "RC", DUMP_BASIC }, + { AR_SCR, "SCR", DUMP_BASIC }, + { AR_INTPEND, "INTPEND", DUMP_BASIC }, + { AR_SFR, "SFR", DUMP_BASIC }, + { AR_PCICFG, "PCICFG", DUMP_BASIC }, + { AR_GPIOCR, "GPIOCR", DUMP_BASIC }, + { AR_GPIODO, "GPIODO", DUMP_BASIC }, + { AR_GPIODI, "GPIODI", DUMP_BASIC }, + { AR_SREV, "SREV", DUMP_BASIC }, + + { AR_PCIE_PMC, "PCIEPMC", DUMP_BASIC, SREV(4,8), SREV(13,7) }, + { AR_PCIE_SERDES, "SERDES", DUMP_BASIC, SREV(4,8), SREV(13,7) }, + { AR_PCIE_SERDES2, "SERDES2", DUMP_BASIC, SREV(4,8), SREV(13,7) }, +#if 0 + { AR_EEPROM_ADDR, "EEADDR", DUMP_BASIC }, + { AR_EEPROM_DATA, "EEDATA", DUMP_BASIC }, + { AR_EEPROM_CMD, "EECMD", DUMP_BASIC }, + { AR_EEPROM_STS, "EESTS", DUMP_BASIC }, + { AR_EEPROM_CFG, "EECFG", DUMP_BASIC }, +#endif + { AR_STA_ID0, "STA_ID0", DUMP_BASIC }, + { AR_STA_ID1, "STA_ID1", DUMP_BASIC | DUMP_KEYCACHE }, + { AR_BSS_ID0, "BSS_ID0", DUMP_BASIC }, + { AR_BSS_ID1, "BSS_ID1", DUMP_BASIC }, + { AR_SLOT_TIME, "SLOTTIME", DUMP_BASIC }, + { AR_TIME_OUT, "TIME_OUT", DUMP_BASIC }, + { AR_RSSI_THR, "RSSI_THR", DUMP_BASIC }, + { AR_USEC, "USEC", DUMP_BASIC }, + { AR_BEACON, "BEACON", DUMP_BASIC }, + { AR_CFP_PERIOD, "CFP_PER", DUMP_BASIC }, + { AR_TIMER0, "TIMER0", DUMP_BASIC }, + { AR_TIMER1, "TIMER1", DUMP_BASIC }, + { AR_TIMER2, "TIMER2", DUMP_BASIC }, + { AR_TIMER3, "TIMER3", DUMP_BASIC }, + { AR_CFP_DUR, "CFP_DUR", DUMP_BASIC }, + { AR_RX_FILTER, "RXFILTER", DUMP_BASIC }, + { AR_MCAST_FIL0, "MCAST_0", DUMP_BASIC }, + { AR_MCAST_FIL1, "MCAST_1", DUMP_BASIC }, + { AR_DIAG_SW, "DIAG_SW", DUMP_BASIC }, + { AR_TSF_L32, "TSF_L32", DUMP_BASIC }, + { AR_TSF_U32, "TSF_U32", DUMP_BASIC }, + { AR_TST_ADDAC, "TST_ADAC", DUMP_BASIC }, + { AR_DEF_ANTENNA, "DEF_ANT", DUMP_BASIC }, + { AR_QOS_MASK, "QOS_MASK", DUMP_BASIC }, + { AR_SEQ_MASK, "SEQ_MASK", DUMP_BASIC }, + { AR_OBSERV_2, "OBSERV2", DUMP_BASIC }, + { AR_OBSERV_1, "OBSERV1", DUMP_BASIC }, + + { AR_LAST_TSTP, "LAST_TST", DUMP_BASIC }, + { AR_NAV, "NAV", DUMP_BASIC }, + { AR_RTS_OK, "RTS_OK", DUMP_BASIC }, + { AR_RTS_FAIL, "RTS_FAIL", DUMP_BASIC }, + { AR_ACK_FAIL, "ACK_FAIL", DUMP_BASIC }, + { AR_FCS_FAIL, "FCS_FAIL", DUMP_BASIC }, + { AR_BEACON_CNT, "BEAC_CNT", DUMP_BASIC }, + + { AR_SLEEP1, "SLEEP1", DUMP_BASIC }, + { AR_SLEEP2, "SLEEP2", DUMP_BASIC }, + { AR_SLEEP3, "SLEEP3", DUMP_BASIC }, + { AR_BSSMSKL, "BSSMSKL", DUMP_BASIC }, + { AR_BSSMSKU, "BSSMSKU", DUMP_BASIC }, + { AR_TPC, "TPC", DUMP_BASIC }, + { AR_TFCNT, "TFCNT", DUMP_BASIC }, + { AR_RFCNT, "RFCNT", DUMP_BASIC }, + { AR_RCCNT, "RCCNT", DUMP_BASIC }, + { AR_CCCNT, "CCCNT", DUMP_BASIC }, + { AR_QUIET1, "QUIET1", DUMP_BASIC }, + { AR_QUIET2, "QUIET2", DUMP_BASIC }, + { AR_TSF_PARM, "TSF_PARM", DUMP_BASIC }, + { AR_NOACK, "NOACK", DUMP_BASIC }, + { AR_PHY_ERR, "PHY_ERR", DUMP_BASIC }, + { AR_QOS_CONTROL, "QOS_CTRL", DUMP_BASIC }, + { AR_QOS_SELECT, "QOS_SEL", DUMP_BASIC }, + { AR_MISC_MODE, "MISCMODE", DUMP_BASIC }, + { AR_FILTOFDM, "FILTOFDM", DUMP_BASIC }, + { AR_FILTCCK, "FILTCCK", DUMP_BASIC }, + { AR_PHYCNT1, "PHYCNT1", DUMP_BASIC }, + { AR_PHYCNTMASK1, "PHYCMSK1", DUMP_BASIC }, + { AR_PHYCNT2, "PHYCNT2", DUMP_BASIC }, + { AR_PHYCNTMASK2, "PHYCMSK2", DUMP_BASIC }, + + /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */ +}; + +static __constructor void +ar5212_ctor(void) +{ + register_regs(ar5212regs, N(ar5212regs), MAC5212, PHYANY); + register_keycache(128, MAC5212, PHYANY); + + register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5212, PHYANY); + register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5212, PHYANY); + register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5212, PHYANY); + register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5212, PHYANY); + register_range(0xa258, 0xa26c, DUMP_BASEBAND, + SREV(7,8), SREV(15,15), PHYANY); +} diff --git a/tools/tools/ath/athregs/dumpregs_5416.c b/tools/tools/ath/athregs/dumpregs_5416.c new file mode 100644 index 000000000000..92fd7697c1a3 --- /dev/null +++ b/tools/tools/ath/athregs/dumpregs_5416.c @@ -0,0 +1,379 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include "diag.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ar5416/ar5416reg.h" +#include "ar5416/ar5416phy.h" + +#include "dumpregs.h" + +#define N(a) (sizeof(a) / sizeof(a[0])) + +#define MAC5416 SREV(13,8), SREV(0xff,0xff) /* XXX */ + +static struct dumpreg ar5416regs[] = { + { AR_CR, "CR", DUMP_BASIC }, + { AR_RXDP, "RXDP", DUMP_BASIC }, + { AR_CFG, "CFG", DUMP_BASIC }, + { AR_MIRT, "MIRT", DUMP_BASIC }, + { AR_TIMT, "TIMT", DUMP_BASIC }, + { AR_CST, "CST", DUMP_BASIC }, + { AR_IER, "IER", DUMP_BASIC }, + { AR_TXCFG, "TXCFG", DUMP_BASIC }, + { AR_RXCFG, "RXCFG", DUMP_BASIC }, + { AR_MIBC, "MIBC", DUMP_BASIC }, + { AR_TOPS, "TOPS", DUMP_BASIC }, + { AR_RXNPTO, "RXNPTO", DUMP_BASIC }, + { AR_TXNPTO, "TXNPTO", DUMP_BASIC }, + { AR_RPGTO, "RPGTO", DUMP_BASIC }, + { AR_RPCNT, "RPCNT", DUMP_BASIC }, + { AR_MACMISC, "MACMISC", DUMP_BASIC }, + { AR_SPC_0, "SPC_0", DUMP_BASIC }, + { AR_SPC_1, "SPC_1", DUMP_BASIC }, + { AR_GTXTO, "GTXTO", DUMP_BASIC }, + { AR_GTTM, "GTTM", DUMP_BASIC }, + + { AR_ISR, "ISR", DUMP_INTERRUPT }, + { AR_ISR_S0, "ISR_S0", DUMP_INTERRUPT }, + { AR_ISR_S1, "ISR_S1", DUMP_INTERRUPT }, + { AR_ISR_S2, "ISR_S2", DUMP_INTERRUPT }, + { AR_ISR_S3, "ISR_S3", DUMP_INTERRUPT }, + { AR_ISR_S4, "ISR_S4", DUMP_INTERRUPT }, + { AR_IMR, "IMR", DUMP_INTERRUPT }, + { AR_IMR_S0, "IMR_S0", DUMP_INTERRUPT }, + { AR_IMR_S1, "IMR_S1", DUMP_INTERRUPT }, + { AR_IMR_S2, "IMR_S2", DUMP_INTERRUPT }, + { AR_IMR_S3, "IMR_S3", DUMP_INTERRUPT }, + { AR_IMR_S4, "IMR_S4", DUMP_INTERRUPT }, +#if 0 + /* NB: don't read the RAC so we don't affect operation */ + { AR_ISR_RAC, "ISR_RAC", DUMP_INTERRUPT }, +#endif + { AR_ISR_S0_S, "ISR_S0_S", DUMP_INTERRUPT }, + { AR_ISR_S1_S, "ISR_S1_S", DUMP_INTERRUPT }, + { AR_ISR_S2_S, "ISR_S2_S", DUMP_INTERRUPT }, + { AR_ISR_S3_S, "ISR_S3_S", DUMP_INTERRUPT }, + { AR_ISR_S4_S, "ISR_S4_S", DUMP_INTERRUPT }, + + { AR_DMADBG_0, "DMADBG0", DUMP_BASIC }, + { AR_DMADBG_1, "DMADBG1", DUMP_BASIC }, + { AR_DMADBG_2, "DMADBG2", DUMP_BASIC }, + { AR_DMADBG_3, "DMADBG3", DUMP_BASIC }, + { AR_DMADBG_4, "DMADBG4", DUMP_BASIC }, + { AR_DMADBG_5, "DMADBG5", DUMP_BASIC }, + { AR_DMADBG_6, "DMADBG6", DUMP_BASIC }, + { AR_DMADBG_7, "DMADBG7", DUMP_BASIC }, + + { AR_DCM_A, "DCM_A", DUMP_BASIC }, + { AR_DCM_D, "DCM_D", DUMP_BASIC }, + { AR_DCCFG, "DCCFG", DUMP_BASIC }, + { AR_CCFG, "CCFG", DUMP_BASIC }, + { AR_CCUCFG, "CCUCFG", DUMP_BASIC }, + { AR_CPC_0, "CPC0", DUMP_BASIC }, + { AR_CPC_1, "CPC1", DUMP_BASIC }, + { AR_CPC_2, "CPC2", DUMP_BASIC }, + { AR_CPC_3, "CPC3", DUMP_BASIC }, + { AR_CPCOVF, "CPCOVF", DUMP_BASIC }, + + { AR_Q0_TXDP, "Q0_TXDP", DUMP_QCU }, + { AR_Q1_TXDP, "Q1_TXDP", DUMP_QCU }, + { AR_Q2_TXDP, "Q2_TXDP", DUMP_QCU }, + { AR_Q3_TXDP, "Q3_TXDP", DUMP_QCU }, + { AR_Q4_TXDP, "Q4_TXDP", DUMP_QCU }, + { AR_Q5_TXDP, "Q5_TXDP", DUMP_QCU }, + { AR_Q6_TXDP, "Q6_TXDP", DUMP_QCU }, + { AR_Q7_TXDP, "Q7_TXDP", DUMP_QCU }, + { AR_Q8_TXDP, "Q8_TXDP", DUMP_QCU }, + { AR_Q9_TXDP, "Q9_TXDP", DUMP_QCU }, + + { AR_Q_TXE, "Q_TXE", DUMP_QCU }, + { AR_Q_TXD, "Q_TXD", DUMP_QCU }, + + { AR_Q0_CBRCFG, "Q0_CBR", DUMP_QCU }, + { AR_Q1_CBRCFG, "Q1_CBR", DUMP_QCU }, + { AR_Q2_CBRCFG, "Q2_CBR", DUMP_QCU }, + { AR_Q3_CBRCFG, "Q3_CBR", DUMP_QCU }, + { AR_Q4_CBRCFG, "Q4_CBR", DUMP_QCU }, + { AR_Q5_CBRCFG, "Q5_CBR", DUMP_QCU }, + { AR_Q6_CBRCFG, "Q6_CBR", DUMP_QCU }, + { AR_Q7_CBRCFG, "Q7_CBR", DUMP_QCU }, + { AR_Q8_CBRCFG, "Q8_CBR", DUMP_QCU }, + { AR_Q9_CBRCFG, "Q9_CBR", DUMP_QCU }, + + { AR_Q0_RDYTIMECFG, "Q0_RDYT", DUMP_QCU }, + { AR_Q1_RDYTIMECFG, "Q1_RDYT", DUMP_QCU }, + { AR_Q2_RDYTIMECFG, "Q2_RDYT", DUMP_QCU }, + { AR_Q3_RDYTIMECFG, "Q3_RDYT", DUMP_QCU }, + { AR_Q4_RDYTIMECFG, "Q4_RDYT", DUMP_QCU }, + { AR_Q5_RDYTIMECFG, "Q5_RDYT", DUMP_QCU }, + { AR_Q6_RDYTIMECFG, "Q6_RDYT", DUMP_QCU }, + { AR_Q7_RDYTIMECFG, "Q7_RDYT", DUMP_QCU }, + { AR_Q8_RDYTIMECFG, "Q8_RDYT", DUMP_QCU }, + { AR_Q9_RDYTIMECFG, "Q9_RDYT", DUMP_QCU }, + + { AR_Q_ONESHOTARM_SC,"Q_ONESHOTARM_SC", DUMP_QCU }, + { AR_Q_ONESHOTARM_CC,"Q_ONESHOTARM_CC", DUMP_QCU }, + + { AR_Q0_MISC, "Q0_MISC", DUMP_QCU }, + { AR_Q1_MISC, "Q1_MISC", DUMP_QCU }, + { AR_Q2_MISC, "Q2_MISC", DUMP_QCU }, + { AR_Q3_MISC, "Q3_MISC", DUMP_QCU }, + { AR_Q4_MISC, "Q4_MISC", DUMP_QCU }, + { AR_Q5_MISC, "Q5_MISC", DUMP_QCU }, + { AR_Q6_MISC, "Q6_MISC", DUMP_QCU }, + { AR_Q7_MISC, "Q7_MISC", DUMP_QCU }, + { AR_Q8_MISC, "Q8_MISC", DUMP_QCU }, + { AR_Q9_MISC, "Q9_MISC", DUMP_QCU }, + + { AR_Q0_STS, "Q0_STS", DUMP_QCU }, + { AR_Q1_STS, "Q1_STS", DUMP_QCU }, + { AR_Q2_STS, "Q2_STS", DUMP_QCU }, + { AR_Q3_STS, "Q3_STS", DUMP_QCU }, + { AR_Q4_STS, "Q4_STS", DUMP_QCU }, + { AR_Q5_STS, "Q5_STS", DUMP_QCU }, + { AR_Q6_STS, "Q6_STS", DUMP_QCU }, + { AR_Q7_STS, "Q7_STS", DUMP_QCU }, + { AR_Q8_STS, "Q8_STS", DUMP_QCU }, + { AR_Q9_STS, "Q9_STS", DUMP_QCU }, + + { AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD", DUMP_QCU }, + + { AR_Q_CBBS, "Q_CBBS", DUMP_QCU }, + { AR_Q_CBBA, "Q_CBBA", DUMP_QCU }, + { AR_Q_CBC, "Q_CBC", DUMP_QCU }, + + { AR_D0_QCUMASK, "D0_MASK", DUMP_DCU }, + { AR_D1_QCUMASK, "D1_MASK", DUMP_DCU }, + { AR_D2_QCUMASK, "D2_MASK", DUMP_DCU }, + { AR_D3_QCUMASK, "D3_MASK", DUMP_DCU }, + { AR_D4_QCUMASK, "D4_MASK", DUMP_DCU }, + { AR_D5_QCUMASK, "D5_MASK", DUMP_DCU }, + { AR_D6_QCUMASK, "D6_MASK", DUMP_DCU }, + { AR_D7_QCUMASK, "D7_MASK", DUMP_DCU }, + { AR_D8_QCUMASK, "D8_MASK", DUMP_DCU }, + { AR_D9_QCUMASK, "D9_MASK", DUMP_DCU }, + + { AR_D0_LCL_IFS, "D0_IFS", DUMP_DCU }, + { AR_D1_LCL_IFS, "D1_IFS", DUMP_DCU }, + { AR_D2_LCL_IFS, "D2_IFS", DUMP_DCU }, + { AR_D3_LCL_IFS, "D3_IFS", DUMP_DCU }, + { AR_D4_LCL_IFS, "D4_IFS", DUMP_DCU }, + { AR_D5_LCL_IFS, "D5_IFS", DUMP_DCU }, + { AR_D6_LCL_IFS, "D6_IFS", DUMP_DCU }, + { AR_D7_LCL_IFS, "D7_IFS", DUMP_DCU }, + { AR_D8_LCL_IFS, "D8_IFS", DUMP_DCU }, + { AR_D9_LCL_IFS, "D9_IFS", DUMP_DCU }, + + { AR_D0_RETRY_LIMIT,"D0_RTRY", DUMP_DCU }, + { AR_D1_RETRY_LIMIT,"D1_RTRY", DUMP_DCU }, + { AR_D2_RETRY_LIMIT,"D2_RTRY", DUMP_DCU }, + { AR_D3_RETRY_LIMIT,"D3_RTRY", DUMP_DCU }, + { AR_D4_RETRY_LIMIT,"D4_RTRY", DUMP_DCU }, + { AR_D5_RETRY_LIMIT,"D5_RTRY", DUMP_DCU }, + { AR_D6_RETRY_LIMIT,"D6_RTRY", DUMP_DCU }, + { AR_D7_RETRY_LIMIT,"D7_RTRY", DUMP_DCU }, + { AR_D8_RETRY_LIMIT,"D8_RTRY", DUMP_DCU }, + { AR_D9_RETRY_LIMIT,"D9_RTRY", DUMP_DCU }, + + { AR_D0_CHNTIME, "D0_CHNT", DUMP_DCU }, + { AR_D1_CHNTIME, "D1_CHNT", DUMP_DCU }, + { AR_D2_CHNTIME, "D2_CHNT", DUMP_DCU }, + { AR_D3_CHNTIME, "D3_CHNT", DUMP_DCU }, + { AR_D4_CHNTIME, "D4_CHNT", DUMP_DCU }, + { AR_D5_CHNTIME, "D5_CHNT", DUMP_DCU }, + { AR_D6_CHNTIME, "D6_CHNT", DUMP_DCU }, + { AR_D7_CHNTIME, "D7_CHNT", DUMP_DCU }, + { AR_D8_CHNTIME, "D8_CHNT", DUMP_DCU }, + { AR_D9_CHNTIME, "D9_CHNT", DUMP_DCU }, + + { AR_D0_MISC, "D0_MISC", DUMP_DCU }, + { AR_D1_MISC, "D1_MISC", DUMP_DCU }, + { AR_D2_MISC, "D2_MISC", DUMP_DCU }, + { AR_D3_MISC, "D3_MISC", DUMP_DCU }, + { AR_D4_MISC, "D4_MISC", DUMP_DCU }, + { AR_D5_MISC, "D5_MISC", DUMP_DCU }, + { AR_D6_MISC, "D6_MISC", DUMP_DCU }, + { AR_D7_MISC, "D7_MISC", DUMP_DCU }, + { AR_D8_MISC, "D8_MISC", DUMP_DCU }, + { AR_D9_MISC, "D9_MISC", DUMP_DCU }, + + { AR_D_SEQNUM, "D_SEQ", DUMP_BASIC | DUMP_DCU }, + { AR_D_GBL_IFS_SIFS,"D_SIFS", DUMP_BASIC }, + { AR_D_GBL_IFS_SLOT,"D_SLOT", DUMP_BASIC }, + { AR_D_GBL_IFS_EIFS,"D_EIFS", DUMP_BASIC }, + { AR_D_GBL_IFS_MISC,"D_MISC", DUMP_BASIC }, + { AR_D_FPCTL, "D_FPCTL", DUMP_BASIC }, + { AR_D_TXPSE, "D_TXPSE", DUMP_BASIC }, +#if 0 + { AR_D_TXBLK_CMD, "D_CMD", DUMP_BASIC }, + { AR_D_TXBLK_DATA, "D_DATA", DUMP_BASIC }, + { AR_D_TXBLK_CLR, "D_CLR", DUMP_BASIC }, + { AR_D_TXBLK_SET, "D_SET", DUMP_BASIC }, +#endif + + { AR_MAC_LED, "MAC_LED", DUMP_BASIC }, + { AR_RC, "RC", DUMP_BASIC }, + { AR_SCR, "SCR", DUMP_BASIC }, + { AR_INTPEND, "INTPEND", DUMP_BASIC }, + { AR_SFR, "SFR", DUMP_BASIC }, + { AR_PCICFG, "PCICFG", DUMP_BASIC }, + { AR_SREV, "SREV", DUMP_BASIC }, + + { AR_AHB_MODE, "AHBMODE", DUMP_BASIC }, + { AR5416_PCIE_PM_CTRL,"PCIEPMC", DUMP_BASIC }, + { AR5416_PCIE_SERDES,"SERDES", DUMP_BASIC }, + { AR5416_PCIE_SERDES2, "SERDES2", DUMP_BASIC }, + + { AR_INTR_ASYNC_MASK,"IASYNCM", DUMP_BASIC }, + { AR_INTR_SYNC_MASK,"ISYNCM", DUMP_BASIC }, + { AR_RTC_RC, "RTC_RC", DUMP_BASIC }, + { AR_RTC_PLL_CONTROL,"RTC_PLL", DUMP_BASIC }, + + { AR_GPIO_IN, "GPIOIN", DUMP_BASIC }, + { AR_GPIO_INTR_OUT, "GPIOINO", DUMP_BASIC }, + { AR_OBS, "OBS", DUMP_BASIC }, +#if 0 + { AR_EEPROM_ADDR, "EEADDR", DUMP_BASIC }, + { AR_EEPROM_DATA, "EEDATA", DUMP_BASIC }, + { AR_EEPROM_CMD, "EECMD", DUMP_BASIC }, + { AR_EEPROM_STS, "EESTS", DUMP_BASIC }, + { AR_EEPROM_CFG, "EECFG", DUMP_BASIC }, +#endif + { AR_STA_ID0, "STA_ID0", DUMP_BASIC }, + { AR_STA_ID1, "STA_ID1", DUMP_BASIC | DUMP_KEYCACHE }, + { AR_BSS_ID0, "BSS_ID0", DUMP_BASIC }, + { AR_BSS_ID1, "BSS_ID1", DUMP_BASIC }, + { AR_SLOT_TIME, "SLOTTIME", DUMP_BASIC }, + { AR_TIME_OUT, "TIME_OUT", DUMP_BASIC }, + { AR_RSSI_THR, "RSSI_THR", DUMP_BASIC }, + { AR_USEC, "USEC", DUMP_BASIC }, + { AR_BEACON, "BEACON", DUMP_BASIC }, + { AR_CFP_PERIOD, "CFP_PER", DUMP_BASIC }, + { AR_TIMER0, "TIMER0", DUMP_BASIC }, + { AR_TIMER1, "TIMER1", DUMP_BASIC }, + { AR_TIMER2, "TIMER2", DUMP_BASIC }, + { AR_TIMER3, "TIMER3", DUMP_BASIC }, + { AR_CFP_DUR, "CFP_DUR", DUMP_BASIC }, + { AR_RX_FILTER, "RXFILTER", DUMP_BASIC }, + { AR_MCAST_FIL0, "MCAST_0", DUMP_BASIC }, + { AR_MCAST_FIL1, "MCAST_1", DUMP_BASIC }, + { AR_DIAG_SW, "DIAG_SW", DUMP_BASIC }, + { AR_TSF_L32, "TSF_L32", DUMP_BASIC }, + { AR_TSF_U32, "TSF_U32", DUMP_BASIC }, + { AR_TST_ADDAC, "TST_ADAC", DUMP_BASIC }, + { AR_DEF_ANTENNA, "DEF_ANT", DUMP_BASIC }, + { AR_QOS_MASK, "QOS_MASK", DUMP_BASIC }, + { AR_SEQ_MASK, "SEQ_MASK", DUMP_BASIC }, + { AR_OBSERV_2, "OBSERV2", DUMP_BASIC }, + { AR_OBSERV_1, "OBSERV1", DUMP_BASIC }, + + { AR_LAST_TSTP, "LAST_TST", DUMP_BASIC }, + { AR_NAV, "NAV", DUMP_BASIC }, + { AR_RTS_OK, "RTS_OK", DUMP_BASIC }, + { AR_RTS_FAIL, "RTS_FAIL", DUMP_BASIC }, + { AR_ACK_FAIL, "ACK_FAIL", DUMP_BASIC }, + { AR_FCS_FAIL, "FCS_FAIL", DUMP_BASIC }, + { AR_BEACON_CNT, "BEAC_CNT", DUMP_BASIC }, + + { AR_SLEEP1, "SLEEP1", DUMP_BASIC }, + { AR_SLEEP2, "SLEEP2", DUMP_BASIC }, + { AR_SLEEP3, "SLEEP3", DUMP_BASIC }, + { AR_BSSMSKL, "BSSMSKL", DUMP_BASIC }, + { AR_BSSMSKU, "BSSMSKU", DUMP_BASIC }, + { AR_TPC, "TPC", DUMP_BASIC }, + { AR_TFCNT, "TFCNT", DUMP_BASIC }, + { AR_RFCNT, "RFCNT", DUMP_BASIC }, + { AR_RCCNT, "RCCNT", DUMP_BASIC }, + { AR_CCCNT, "CCCNT", DUMP_BASIC }, + { AR_QUIET1, "QUIET1", DUMP_BASIC }, + { AR_QUIET2, "QUIET2", DUMP_BASIC }, + { AR_TSF_PARM, "TSF_PARM", DUMP_BASIC }, + { AR_NOACK, "NOACK", DUMP_BASIC }, + { AR_PHY_ERR, "PHY_ERR", DUMP_BASIC }, + { AR_QOS_CONTROL, "QOS_CTRL", DUMP_BASIC }, + { AR_QOS_SELECT, "QOS_SEL", DUMP_BASIC }, + { AR_MISC_MODE, "MISCMODE", DUMP_BASIC }, + { AR_FILTOFDM, "FILTOFDM", DUMP_BASIC }, + { AR_FILTCCK, "FILTCCK", DUMP_BASIC }, + { AR_PHYCNT1, "PHYCNT1", DUMP_BASIC }, + { AR_PHYCNTMASK1, "PHYCMSK1", DUMP_BASIC }, + { AR_PHYCNT2, "PHYCNT2", DUMP_BASIC }, + { AR_PHYCNTMASK2, "PHYCMSK2", DUMP_BASIC }, + + { AR_TXOP_X, "TXOPX", DUMP_BASIC }, + { AR_NEXT_TBTT, "NXTTBTT", DUMP_BASIC}, + { AR_NEXT_DBA, "NXTDBA", DUMP_BASIC }, + { AR_NEXT_SWBA, "NXTSWBA", DUMP_BASIC }, + { AR_NEXT_CFP, "NXTCFP", DUMP_BASIC }, + { AR_NEXT_HCF, "NXTHCF", DUMP_BASIC }, + { AR_NEXT_DTIM, "NXTDTIM", DUMP_BASIC }, + { AR_NEXT_QUIET, "NXTQUIET", DUMP_BASIC }, + { AR_NEXT_NDP, "NXTNDP", DUMP_BASIC }, + { AR5416_BEACON_PERIOD, "BCNPER", DUMP_BASIC }, + { AR_DBA_PERIOD, "DBAPER", DUMP_BASIC }, + { AR_SWBA_PERIOD, "SWBAPER", DUMP_BASIC }, + { AR_TIM_PERIOD, "TIMPER", DUMP_BASIC }, + { AR_DTIM_PERIOD, "DTIMPER", DUMP_BASIC }, + { AR_QUIET_PERIOD, "QUIETPER", DUMP_BASIC }, + { AR_NDP_PERIOD, "NDPPER", DUMP_BASIC }, + { AR_TIMER_MODE, "TIMERMOD", DUMP_BASIC }, + { AR_2040_MODE, "2040MODE", DUMP_BASIC }, + { AR_PCU_TXBUF_CTRL,"PCUTXBUF", DUMP_BASIC }, + { AR_SLP32_MODE, "SLP32MOD", DUMP_BASIC }, + { AR_SLP32_WAKE, "SLP32WAK", DUMP_BASIC }, + { AR_SLP32_INC, "SLP32INC", DUMP_BASIC }, + { AR_SLP_CNT, "SLPCNT", DUMP_BASIC }, + { AR_SLP_MIB_CTRL, "SLPMIB", DUMP_BASIC }, + { AR_EXTRCCNT, "EXTRCCNT", DUMP_BASIC }, + + /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */ +}; + +static __constructor void +ar5416_ctor(void) +{ + register_regs(ar5416regs, N(ar5416regs), MAC5416, PHYANY); + register_keycache(128, MAC5416, PHYANY); + + register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0x9900, 0x997c, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0x99a4, 0x99a4, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xa258, 0xa26c, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xa3c8, 0xa3d4, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xa864, 0xa864, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xa9bc, 0xa9bc, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xb864, 0xb864, DUMP_BASEBAND, MAC5416, PHYANY); + register_range(0xb9bc, 0xb9bc, DUMP_BASEBAND, MAC5416, PHYANY); +} diff --git a/tools/tools/ath/athstats/Makefile b/tools/tools/ath/athstats/Makefile index 036eaaae9b36..cd05e96cb56d 100644 --- a/tools/tools/ath/athstats/Makefile +++ b/tools/tools/ath/athstats/Makefile @@ -1,8 +1,6 @@ # $FreeBSD$ PROG= athstats -BINDIR= /usr/local/bin -NO_MAN= SRCS= main.c statfoo.c athstats.c @@ -15,9 +13,9 @@ CLEANFILES+= opt_ah.h ah_osdep.h CFLAGS+=-DATH_SUPPORT_ANI CFLAGS+=-I${.CURDIR} -CFLAGS+=-I${SRCDIR}/sys/contrib/dev/ath CFLAGS+=-I${SRCDIR}/sys/net80211 -CFLAGS+=-I${SRCDIR}/sys/dev/ath + +.include <../Makefile.inc> athstats.o: opt_ah.h ah_osdep.h diff --git a/tools/tools/ath/common/ah_osdep.h b/tools/tools/ath/common/ah_osdep.h new file mode 100644 index 000000000000..047811159a42 --- /dev/null +++ b/tools/tools/ath/common/ah_osdep.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#ifndef _ATH_AH_OSDEP_H_ +#define _ATH_AH_OSDEP_H_ +/* + * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. + */ +#include + +/* + * Bus i/o type definitions. + */ +typedef void *HAL_SOFTC; +typedef int HAL_BUS_TAG; +typedef void *HAL_BUS_HANDLE; + +#define OS_DELAY(_n) DELAY(_n) +#define OS_INLINE __inline +#define OS_MEMZERO(_a, _size) bzero((_a), (_size)) +#define OS_MEMCPY(_dst, _src, _size) bcopy((_src), (_dst), (_size)) +#define OS_MACEQU(_a, _b) \ + (bcmp((_a), (_b), IEEE80211_ADDR_LEN) == 0) + +struct ath_hal; +extern u_int32_t OS_GETUPTIME(struct ath_hal *); +extern void OS_REG_WRITE(struct ath_hal *, u_int32_t, u_int32_t); +extern u_int32_t OS_REG_READ(struct ath_hal *, u_int32_t); +extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); +#define OS_GETUPTIME(_ah) 0 +#define OS_REG_WRITE(_ah, _reg, _val) +#define OS_REG_READ(_ah, _reg) 0 +#define OS_MARK(_ah, _id, _v) +#define __packed __attribute__((__packed__)) + +/* + * Linux/BSD gcc compatibility shims. + */ +#ifndef __printflike +#define __printflike(_a,_b) \ + __attribute__ ((__format__ (__printf__, _a, _b))) +#endif +#include +#ifndef __va_list +#define __va_list va_list +#endif +#define OS_INLINE __inline +#endif /* _ATH_AH_OSDEP_H_ */ diff --git a/tools/tools/ath/common/diag.h b/tools/tools/ath/common/diag.h new file mode 100644 index 000000000000..8c0c1a7f1c4b --- /dev/null +++ b/tools/tools/ath/common/diag.h @@ -0,0 +1,61 @@ +#ifndef _DIAG_ +#define _DIAG_ +/*- + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ +#include +#include +#include +#include +#include +#include + +#include +#include "if_athioctl.h" + +struct statshandler { + u_long interval; + void *total; + void *cur; + + void (*getstats)(struct statshandler *, void *); + void (*update)(struct statshandler *); + + void (*printbanner)(struct statshandler *, FILE *); + void (*reportdelta)(struct statshandler *, FILE *); + void (*reporttotal)(struct statshandler *, FILE *); + void (*reportverbose)(struct statshandler *, FILE *); +}; + +extern void reportstats(FILE *fd, struct statshandler *sh); +extern void runstats(FILE *fd, struct statshandler *sh); +extern void reportcol(FILE *fd, u_int32_t v, const char *def_fmt, + u_int32_t max, const char *alt_fmt); +#endif /* _DIAG_ */