riscv/sifive: add FU540 SPI controller driver
Initial working prototype of the Serial Peripheral Interface controller in the SiFive FU540 SoC. Reviewed by: kp Sponsored by: Axiado
This commit is contained in:
Philip Paeps
parent
09728b2df6
commit
109ece57d0
@ -1,3 +1,4 @@
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# $FreeBSD$
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riscv/sifive/fu540_prci.c standard
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riscv/sifive/fu540_spi.c optional fu540spi spibus
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403
sys/riscv/sifive/fu540_spi.c
Normal file
403
sys/riscv/sifive/fu540_spi.c
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@ -0,0 +1,403 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Axiado Corporation
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* All rights reserved.
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*
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* This software was developed in part by Philip Paeps and Kristof Provost
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* under contract for Axiado Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include "spibus_if.h"
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#if 1
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#define DBGPRINT(dev, fmt, args...) \
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device_printf(dev, "%s: " fmt "\n", __func__, ## args)
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#else
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#define DBGPRINT(dev, fmt, args...)
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#endif
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static struct resource_spec fuspi_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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RESOURCE_SPEC_END
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};
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struct fuspi_softc {
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device_t dev;
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device_t parent;
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struct mtx mtx;
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struct resource *res;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih;
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clk_t clk;
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uint32_t cs_max;
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};
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#define FUSPI_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define FUSPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define FUSPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
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#define FUSPI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
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/*
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* Register offsets.
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* From Sifive-Unleashed-FU540-C000-v1.0.pdf page 101.
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*/
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#define FUSPI_REG_SCKDIV 0x00 /* Serial clock divisor */
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#define FUSPI_REG_SCKMODE 0x04 /* Serial clock mode */
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#define FUSPI_REG_CSID 0x10 /* Chip select ID */
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#define FUSPI_REG_CSDEF 0x14 /* Chip select default */
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#define FUSPI_REG_CSMODE 0x18 /* Chip select mode */
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#define FUSPI_REG_DELAY0 0x28 /* Delay control 0 */
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#define FUSPI_REG_DELAY1 0x2C /* Delay control 1 */
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#define FUSPI_REG_FMT 0x40 /* Frame format */
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#define FUSPI_REG_TXDATA 0x48 /* Tx FIFO data */
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#define FUSPI_REG_RXDATA 0x4C /* Rx FIFO data */
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#define FUSPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
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#define FUSPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
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#define FUSPI_REG_FCTRL 0x60 /* SPI flash interface control* */
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#define FUSPI_REG_FFMT 0x64 /* SPI flash instruction format* */
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#define FUSPI_REG_IE 0x70 /* SPI interrupt enable */
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#define FUSPI_REG_IP 0x74 /* SPI interrupt pending */
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#define FUSPI_SCKDIV_MASK 0xfff
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#define FUSPI_CSDEF_ALL ((1 << sc->cs_max)-1)
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#define FUSPI_CSMODE_AUTO 0x0U
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#define FUSPI_CSMODE_HOLD 0x2U
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#define FUSPI_CSMODE_OFF 0x3U
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#define FUSPI_TXDATA_DATA_MASK 0xff
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#define FUSPI_TXDATA_FULL (1 << 31)
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#define FUSPI_RXDATA_DATA_MASK 0xff
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#define FUSPI_RXDATA_EMPTY (1 << 31)
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#define FUSPI_SCKMODE_PHA (1 << 0)
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#define FUSPI_SCKMODE_POL (1 << 1)
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#define FUSPI_FMT_PROTO_SINGLE 0x0U
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#define FUSPI_FMT_PROTO_DUAL 0x1U
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#define FUSPI_FMT_PROTO_QUAD 0x2U
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#define FUSPI_FMT_PROTO_MASK 0x3U
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#define FUSPI_FMT_ENDIAN (1 << 2)
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#define FUSPI_FMT_DIR (1 << 3)
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#define FUSPI_FMT_LEN(x) ((uint32_t)(x) << 16)
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#define FUSPI_FMT_LEN_MASK (0xfU << 16)
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#define FUSPI_FIFO_DEPTH 8
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#define FUSPI_READ(_sc, _reg) \
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bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
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#define FUSPI_WRITE(_sc, _reg, _val) \
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bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
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static void
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fuspi_tx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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{
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uint32_t val;
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uint8_t *p, *end;
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KASSERT(buf != NULL, ("TX buffer cannot be NULL"));
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end = buf + bufsiz;
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for (p = buf; p < end; p++) {
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do {
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val = FUSPI_READ(sc, FUSPI_REG_TXDATA);
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} while (val & FUSPI_TXDATA_FULL);
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val = *p;
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FUSPI_WRITE(sc, FUSPI_REG_TXDATA, val);
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}
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}
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static void
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fuspi_rx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
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{
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uint32_t val;
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uint8_t *p, *end;
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KASSERT(buf != NULL, ("RX buffer cannot be NULL"));
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KASSERT(bufsiz <= FUSPI_FIFO_DEPTH,
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("Cannot receive more than %d bytes at a time\n",
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FUSPI_FIFO_DEPTH));
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end = buf + bufsiz;
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for (p = buf; p < end; p++) {
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do {
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val = FUSPI_READ(sc, FUSPI_REG_RXDATA);
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} while (val & FUSPI_RXDATA_EMPTY);
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*p = val & FUSPI_RXDATA_DATA_MASK;
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};
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}
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static int
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fuspi_xfer_buf(struct fuspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf,
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uint32_t txlen, uint32_t rxlen)
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{
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uint32_t bytes;
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KASSERT(txlen == rxlen, ("TX and RX lengths must be equal"));
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KASSERT(rxbuf != NULL, ("RX buffer cannot be NULL"));
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KASSERT(txbuf != NULL, ("TX buffer cannot be NULL"));
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while (txlen) {
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bytes = (txlen > FUSPI_FIFO_DEPTH) ? FUSPI_FIFO_DEPTH : txlen;
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fuspi_tx(sc, txbuf, bytes);
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txbuf += bytes;
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fuspi_rx(sc, rxbuf, bytes);
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rxbuf += bytes;
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txlen -= bytes;
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}
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return (0);
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}
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static int
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fuspi_setup(struct fuspi_softc *sc, uint32_t cs, uint32_t mode,
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uint32_t freq)
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{
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uint32_t csmode, fmt, sckdiv, sckmode;
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uint64_t clock;
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int ret;
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FUSPI_ASSERT_LOCKED(sc);
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ret = clk_get_freq(sc->clk, &clock);
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if (ret) {
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device_printf(sc->dev, "Cannot get clock frequency: %d\n", ret);
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return (ret);
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}
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/*
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* Fsck = Fin / 2 * (div + 1)
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* -> div = Fin / (2 * Fsck) - 1
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*/
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sckdiv = (howmany(clock >> 1, freq) - 1) & FUSPI_SCKDIV_MASK;
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FUSPI_WRITE(sc, FUSPI_REG_SCKDIV, sckdiv);
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switch (mode) {
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case SPIBUS_MODE_CPHA:
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sckmode = FUSPI_SCKMODE_PHA;
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break;
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case SPIBUS_MODE_CPOL:
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sckmode = FUSPI_SCKMODE_POL;
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break;
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case SPIBUS_MODE_CPOL_CPHA:
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sckmode = FUSPI_SCKMODE_PHA | FUSPI_SCKMODE_POL;
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break;
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}
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FUSPI_WRITE(sc, FUSPI_REG_SCKMODE, sckmode);
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csmode = FUSPI_CSMODE_HOLD;
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if (cs & SPIBUS_CS_HIGH)
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csmode = FUSPI_CSMODE_AUTO;
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FUSPI_WRITE(sc, FUSPI_REG_CSMODE, csmode);
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FUSPI_WRITE(sc, FUSPI_REG_CSID, cs & ~SPIBUS_CS_HIGH);
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fmt = FUSPI_FMT_PROTO_SINGLE | FUSPI_FMT_LEN(8);
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FUSPI_WRITE(sc, FUSPI_REG_FMT, fmt);
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return (0);
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}
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static int
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fuspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct fuspi_softc *sc;
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uint32_t clock, cs, csdef, mode;
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int err;
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("TX and RX command sizes must be equal"));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("TX and RX data sizes must be equal"));
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sc = device_get_softc(dev);
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spibus_get_cs(child, &cs);
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spibus_get_clock(child, &clock);
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spibus_get_mode(child, &mode);
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if (cs > sc->cs_max) {
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device_printf(sc->dev, "Invalid chip select %u\n", cs);
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return (EINVAL);
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}
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FUSPI_LOCK(sc);
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device_busy(sc->dev);
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err = fuspi_setup(sc, cs, mode, clock);
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if (err != 0) {
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FUSPI_UNLOCK(sc);
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return (err);
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}
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err = 0;
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if (cmd->tx_cmd_sz > 0)
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err = fuspi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
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cmd->tx_cmd_sz, cmd->rx_cmd_sz);
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if (cmd->tx_data_sz > 0 && err == 0)
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err = fuspi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
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cmd->tx_data_sz, cmd->rx_data_sz);
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/* Deassert chip select. */
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csdef = FUSPI_CSDEF_ALL & ~(1 << cs);
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FUSPI_WRITE(sc, FUSPI_REG_CSDEF, csdef);
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FUSPI_WRITE(sc, FUSPI_REG_CSDEF, FUSPI_CSDEF_ALL);
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device_unbusy(sc->dev);
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FUSPI_UNLOCK(sc);
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return (err);
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}
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static int
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fuspi_attach(device_t dev)
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{
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struct fuspi_softc *sc;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
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error = bus_alloc_resources(dev, fuspi_spec, &sc->res);
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if (error) {
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device_printf(dev, "Couldn't allocate resources\n");
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goto fail;
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}
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
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if (error) {
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device_printf(dev, "Couldn't allocate clock: %d\n", error);
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goto fail;
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}
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error = clk_enable(sc->clk);
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if (error) {
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device_printf(dev, "Couldn't enable clock: %d\n", error);
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goto fail;
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}
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/*
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* From Sifive-Unleashed-FU540-C000-v1.0.pdf page 103:
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* csdef is cs_width bits wide and all ones on reset.
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*/
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sc->cs_max = FUSPI_READ(sc, FUSPI_REG_CSDEF);
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/*
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* We don't support the direct-mapped flash interface.
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* Disable it.
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*/
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FUSPI_WRITE(sc, FUSPI_REG_FCTRL, 0x0);
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/* Probe and attach the spibus when interrupts are available. */
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sc->parent = device_add_child(dev, "spibus", -1);
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config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
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return (0);
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fail1:
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bus_release_resources(dev, fuspi_spec, &sc->res);
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fail:
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mtx_destroy(&sc->mtx);
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return (error);
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}
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static int
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fuspi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "sifive,spi0"))
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return (ENXIO);
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device_set_desc(dev, "SiFive FU540 SPI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static phandle_t
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fuspi_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static device_method_t fuspi_methods[] = {
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DEVMETHOD(device_probe, fuspi_probe),
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DEVMETHOD(device_attach, fuspi_attach),
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DEVMETHOD(spibus_transfer, fuspi_transfer),
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DEVMETHOD(ofw_bus_get_node, fuspi_get_node),
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DEVMETHOD_END
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};
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static driver_t fuspi_driver = {
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"fu540spi",
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fuspi_methods,
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sizeof(struct fuspi_softc)
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};
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static devclass_t fuspi_devclass;
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DRIVER_MODULE(fu540spi, simplebus, fuspi_driver, fuspi_devclass, 0, 0);
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DRIVER_MODULE(ofw_spibus, fu540spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0);
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MODULE_DEPEND(fu540spi, ofw_spibus, 1, 1, 1);
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