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Introduce pmap_kenter_supersection(), which maps 16MB super-sections into

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the kernel pmap.
Document a bit more the behavior of the xscale core 3.
This commit is contained in:
Olivier Houchard 2007-06-11 21:29:26 +00:00
parent e411ce026a
commit 10d8c18005
3 changed files with 97 additions and 2 deletions
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30
sys/arm/arm/pmap.c
View File

@ -613,11 +613,9 @@ pmap_pte_init_xscale(void)
* is significantly faster than the traditional, write-through
* behavior of this case.
*/
#ifndef CPU_XSCALE_CORE3
pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
#endif
#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
#ifdef XSCALE_CACHE_WRITE_THROUGH
/*
@ -2820,6 +2818,34 @@ pmap_remove_pages(pmap_t pmap)
* Low level mapping routines.....
***************************************************/
/* Map a super section into the KVA. */
void
pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
{
pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_OFFSET) |
(((pa >> 32) & 0x8) << 20) | L1_S_PROT(PTE_KERNEL,
VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
struct l1_ttable *l1;
vm_offset_t va_end;
KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
("Not a valid section mapping"));
if (flags & SECTION_CACHE)
pd |= pte_l1_s_cache_mode;
else if (flags & SECTION_PT)
pd |= pte_l1_s_cache_mode_pt;
va = va & L1_SUP_OFFSET;
va_end = va + L1_SUP_SIZE;
SLIST_FOREACH(l1, &l1_list, l1_link) {
for (; va < va_end; va += L1_S_SIZE) {
l1->l1_kva[L1_IDX(va)] = pd;
PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
}
}
}
/* Map a section into the KVA. */
void

1
sys/arm/include/pmap.h
View File

@ -521,6 +521,7 @@ void pmap_devmap_register(const struct pmap_devmap *);
#define SECTION_CACHE 0x1
#define SECTION_PT 0x2
void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
extern char *_tmppt;

68
sys/arm/include/pte.h
View File

@ -140,6 +140,12 @@ typedef uint32_t pt_entry_t; /* page table entry */
* presented to the translation logic.
*/
/* ARMv6 super-sections. */
#define L1_SUP_SIZE 0x01000000 /* 16M */
#define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
#define L1_SUP_FRAME (~L1_SUP_OFFSET)
#define L1_SUP_SHIFT 24
#define L1_S_SIZE 0x00100000 /* 1M */
#define L1_S_OFFSET (L1_S_SIZE - 1)
#define L1_S_FRAME (~L1_S_OFFSET)
@ -199,10 +205,13 @@ typedef uint32_t pt_entry_t; /* page table entry */
#define L1_S_DOM_MASK L1_S_DOM(0xf)
#define L1_S_AP(x) ((x) << 10) /* access permissions */
#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
#define L1_SHARED (1 << 16)
#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */
#define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */
/* L1 Coarse Descriptor */
#define L1_C_IMP0 0x00000004 /* implementation defined */
#define L1_C_IMP1 0x00000008 /* implementation defined */
@ -250,6 +259,7 @@ typedef uint32_t pt_entry_t; /* page table entry */
#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */
#define L2_XSCALE_L_S(x) (1 << 15) /* Shared */
#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */
/*
@ -296,6 +306,64 @@ typedef uint32_t pt_entry_t; /* page table entry */
* 1 1 Y Y Write-back R/W Allocate
*/
#define TEX_XSCALE_X 0x01 /* X modifies C and B */
#define TEX_XSCALE_E 0x02
#define TEX_XSCALE_T 0x04
/* Xscale core 3 */
/*
*
* Cache attributes with L2 present, S = 0
* T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
* 0 0 0 0 0 N N - N N
* 0 0 0 0 1 N N - N Y
* 0 0 0 1 0 Y Y WT N Y
* 0 0 0 1 1 Y Y WB Y Y
* 0 0 1 0 0 N N - Y Y
* 0 0 1 0 1 N N - N N
* 0 0 1 1 0 Y Y - - N
* 0 0 1 1 1 Y Y WT Y Y
* 0 1 0 0 0 N N - N N
* 0 1 0 0 1 N/A N/A N/A N/A N/A
* 0 1 0 1 0 N/A N/A N/A N/A N/A
* 0 1 0 1 1 N/A N/A N/A N/A N/A
* 0 1 1 X X N/A N/A N/A N/A N/A
* 1 X 0 0 0 N N - N Y
* 1 X 0 0 1 Y N - N Y
* 1 X 0 1 0 Y N - N Y
* 1 X 0 1 1 Y N - Y Y
* 1 X 1 0 0 N N - Y Y
* 1 X 1 0 1 Y Y WT Y Y
* 1 X 1 1 0 Y Y WT Y Y
* 1 X 1 1 1 Y Y WT Y Y
*
*
*
*
* Cache attributes with L2 present, S = 1
* T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
* 0 0 0 0 0 N N - N N
* 0 0 0 0 1 N N - N Y
* 0 0 0 1 0 Y Y - N Y
* 0 0 0 1 1 Y Y WT Y Y
* 0 0 1 0 0 N N - Y Y
* 0 0 1 0 1 N N - N N
* 0 0 1 1 0 Y Y - - N
* 0 0 1 1 1 Y Y WT Y Y
* 0 1 0 0 0 N N - N N
* 0 1 0 0 1 N/A N/A N/A N/A N/A
* 0 1 0 1 0 N/A N/A N/A N/A N/A
* 0 1 0 1 1 N/A N/A N/A N/A N/A
* 0 1 1 X X N/A N/A N/A N/A N/A
* 1 X 0 0 0 N N - N Y
* 1 X 0 0 1 Y N - N Y
* 1 X 0 1 0 Y N - N Y
* 1 X 0 1 1 Y N - Y Y
* 1 X 1 0 0 N N - Y Y
* 1 X 1 0 1 Y Y WT Y Y
* 1 X 1 1 0 Y Y WT Y Y
* 1 X 1 1 1 Y Y WT Y Y
*/
#endif /* !_MACHINE_PTE_H_ */
/* End of pte.h */