From 10e5aeb6eb5aee6f5e68c10e693364fbe36efb48 Mon Sep 17 00:00:00 2001 From: manu Date: Mon, 25 Feb 2019 17:40:00 +0000 Subject: [PATCH] arm64: rockchip: clk: Set the write mask when setting the clock mux RockChip clocks have a write mask in the upper 16bits of the mux register which wasn't set in the set_mux function. Also the wrong parent was tested instead of the real current one, when switch parent, test with the current one before. Pointy Hat: manu MFC after: 1 week --- sys/arm64/rockchip/clk/rk_clk_composite.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/arm64/rockchip/clk/rk_clk_composite.c b/sys/arm64/rockchip/clk/rk_clk_composite.c index bc550a8e766e..1f64dacdeec2 100644 --- a/sys/arm64/rockchip/clk/rk_clk_composite.c +++ b/sys/arm64/rockchip/clk/rk_clk_composite.c @@ -128,7 +128,7 @@ rk_clk_composite_set_mux(struct clknode *clk, int index) READ4(clk, sc->muxdiv_offset, &val); val &= ~sc->mux_mask; val |= index << sc->mux_shift; - WRITE4(clk, sc->muxdiv_offset, val); + WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_COMPOSITE_MASK); DEVICE_UNLOCK(clk); return (0); @@ -222,6 +222,7 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, return (0); } + p_idx = clknode_get_parent_idx(clk); if (p_idx != best_parent) clknode_set_parent_by_idx(clk, best_parent);