- Improve the comment regarding the workaround for the E250 interrupt map
bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
This commit is contained in:
Marius Strobl
parent
1245b3433e
commit
114bfbb64e
@ -33,8 +33,8 @@
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__FBSDID("$FreeBSD$");
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/*
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* Support for `Psycho' and `Psycho+' UPA to PCI bridge and
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* UltraSPARC IIi and IIe `Sabre' PCI controllers
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* Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
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* (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
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*/
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#include "opt_ofw_pci.h"
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@ -188,6 +188,9 @@ struct psycho_clr {
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* the IIi. The APB let's the IIi handle two independednt PCI buses, and
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* appears as two "Simba"'s underneath the Sabre.
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*
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* "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
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* basically the same as Sabre but without an APB underneath it.
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*
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* "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus
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* and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
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* "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
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@ -222,8 +225,8 @@ struct psycho_desc {
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static const struct psycho_desc psycho_compats[] = {
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{ "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
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{ "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" },
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{ "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" },
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{ "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
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{ "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
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{ NULL, 0, NULL }
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};
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@ -373,7 +376,7 @@ psycho_attach(device_t dev)
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sc->sc_bushandle = osc->sc_bushandle;
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}
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csr = PSYCHO_READ8(sc, PSR_CS);
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sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */
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sc->sc_ign = 0x7c0; /* Hummingbird/Sabre IGN is always 0x1f. */
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if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
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sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT;
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@ -392,7 +395,8 @@ psycho_attach(device_t dev)
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/* Use the PROM preset for now. */
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csr = PCICTL_READ8(sc, PCR_TAS);
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if (csr == 0)
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panic("%s: Sabre TAS not initialized.", __func__);
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panic("%s: Hummingbird/Sabre TAS not initialized.",
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__func__);
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dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
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} else
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dvmabase = -1;
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@ -435,8 +439,8 @@ psycho_attach(device_t dev)
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SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
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/*
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* If we're a Sabre or the first of a pair of Psycho's to arrive here,
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* start up the IOMMU.
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* If we're a Hummingbird/Sabre or the first of a pair of Psycho's to
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* arrive here, start up the IOMMU.
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*/
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if (osc == NULL) {
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/*
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@ -458,7 +462,8 @@ psycho_attach(device_t dev)
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/* Psycho-specific initialization */
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if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
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/*
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* Sabres do not have the following two interrupts.
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* Hummingbirds/Sabres do not have the following two
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* interrupts.
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*/
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psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP,
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INTR_FAST, psycho_bus_b);
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@ -496,7 +501,7 @@ psycho_attach(device_t dev)
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sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
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psycho_iommu_init(sc, 3, dvmabase);
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} else {
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/* Just copy IOMMU state, config tag and address */
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/* Just copy IOMMU state, config tag and address. */
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sc->sc_is = osc->sc_is;
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if (OF_getproplen(node, "no-streaming-cache") < 0)
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sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
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@ -558,8 +563,8 @@ psycho_attach(device_t dev)
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* NOTE: for the Psycho, the second write changes the bus number the
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* Psycho itself uses for it's configuration space, so these
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* writes must be kept in this order!
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* The Sabre always uses bus 0, but there only can be one Sabre per
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* machine.
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* The Hummingbird/Sabre always uses bus 0, but there only can be one
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* Hummingbird/Sabre per machine.
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*/
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PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS,
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sc->sc_pci_subbus, 1);
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@ -568,7 +573,13 @@ psycho_attach(device_t dev)
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ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
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/*
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* Workaround for incorrect interrupt map entries on E250.
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* On E250 the interrupt map entry for the EBus bridge is wrong,
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* causing incorrect interrupts to be assigned to some devices on
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* the EBus. Work around it by changing our copy of the interrupt
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* map mask to do perform a full comparison of the INO. That way
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* the interrupt map entry for the EBus bridge won't match at all
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* and the INOs specified in the "interrupts" properties of the
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* EBus devices will be used directly instead.
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*/
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if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
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sc->sc_pci_iinfo.opi_imapmsk != NULL)
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@ -607,7 +618,7 @@ psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr,
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int found;
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found = 0;
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/* Hunt thru obio first */
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/* Hunt thru OBIO first. */
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diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
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for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
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intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8,
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@ -622,7 +633,7 @@ psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr,
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if (!found) {
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diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
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/* Now do PCI interrupts */
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/* Now do PCI interrupts. */
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for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
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intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
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diag >>= 8) {
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@ -222,8 +222,11 @@
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/* what the bits mean! */
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/* PCI [a|b] control/status register */
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/* note that the Sabre only has one set of PCI control/status registers */
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/*
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* PCI [a|b] control/status register
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* Note that the Hummingbird/Sabre only has one set of PCI control/status
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* registers.
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*/
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#define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */
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#define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */
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#define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
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