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MFC: Change the x86 interrupt code to allocate IDT vectors on-demand.

Browse Source 
Approved by:	re (scottl)
This commit is contained in:
jhb 2006-03-01 20:50:10 +00:00
parent f9dfac8905
commit 1169153605
8 changed files with 433 additions and 191 deletions
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152
sys/amd64/amd64/io_apic.c
View File

@ -56,10 +56,10 @@ __FBSDID("$FreeBSD$");
#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
#define VECTOR_EXTINT 252
#define VECTOR_NMI 253
#define VECTOR_SMI 254
#define VECTOR_DISABLED 255
#define IRQ_EXTINT (NUM_IO_INTS + 1)
#define IRQ_NMI (NUM_IO_INTS + 2)
#define IRQ_SMI (NUM_IO_INTS + 3)
#define IRQ_DISABLED (NUM_IO_INTS + 4)
#define DEST_NONE -1
@ -68,22 +68,18 @@ __FBSDID("$FreeBSD$");
static MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures");
/*
* New interrupt support code..
*
* XXX: we really should have the interrupt cookie passed up from new-bus
* just be a int pin, and not map 1:1 to interrupt vector number but should
* use INTR_TYPE_FOO to set priority bands for device classes and do all the
* magic remapping of intpin to vector in here. For now we just cheat as on
* ia64 and map intpin X to vector NRSVIDT + X. Note that we assume that the
* first IO APIC has ISA interrupts on pins 1-15. Not sure how you are
* really supposed to figure out which IO APIC in a system with multiple IO
* APIC's actually has the ISA interrupts routed to it. As far as interrupt
* pin numbers, we use the ACPI System Interrupt number model where each
* IO APIC has a contiguous chunk of the System Interrupt address space.
* I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
* as laid out in the ACPI System Interrupt number model where each I/O
* APIC has a contiguous chunk of the System Interrupt address space.
* We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
* IRQs behave as PCI IRQs by default. We also assume that the pin for
* IRQ 0 is actually an ExtINT pin. The apic enumerators override the
* configuration of individual pins as indicated by their tables.
*/
struct ioapic_intsrc {
struct intsrc io_intsrc;
u_int io_irq;
u_int io_intpin:8;
u_int io_vector:8;
u_int io_activehi:1;
@ -107,7 +103,7 @@ struct ioapic {
static u_int ioapic_read(volatile ioapic_t *apic, int reg);
static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
static const char *ioapic_bus_string(int bus_type);
static void ioapic_print_vector(struct ioapic_intsrc *intpin);
static void ioapic_print_irq(struct ioapic_intsrc *intpin);
static void ioapic_enable_source(struct intsrc *isrc);
static void ioapic_disable_source(struct intsrc *isrc, int eoi);
static void ioapic_eoi_source(struct intsrc *isrc);
@ -178,25 +174,25 @@ ioapic_bus_string(int bus_type)
}
static void
ioapic_print_vector(struct ioapic_intsrc *intpin)
ioapic_print_irq(struct ioapic_intsrc *intpin)
{
switch (intpin->io_vector) {
case VECTOR_DISABLED:
switch (intpin->io_irq) {
case IRQ_DISABLED:
printf("disabled");
break;
case VECTOR_EXTINT:
case IRQ_EXTINT:
printf("ExtINT");
break;
case VECTOR_NMI:
case IRQ_NMI:
printf("NMI");
break;
case VECTOR_SMI:
case IRQ_SMI:
printf("SMI");
break;
default:
printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
intpin->io_vector);
intpin->io_irq);
}
}
@ -259,14 +255,20 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin)
struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
uint32_t low, high, value;
/* For disabled pins, just ensure that they are masked. */
if (intpin->io_vector == VECTOR_DISABLED) {
/*
* If a pin is completely invalid or if it is valid but hasn't
* been enabled yet, just ensure that the pin is masked.
*/
if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
intpin->io_vector == 0)) {
mtx_lock_spin(&icu_lock);
low = ioapic_read(io->io_addr,
IOAPIC_REDTBL_LO(intpin->io_intpin));
if ((low & IOART_INTMASK) == IOART_INTMCLR)
ioapic_write(io->io_addr,
IOAPIC_REDTBL_LO(intpin->io_intpin),
low | IOART_INTMSET);
mtx_unlock_spin(&icu_lock);
return;
}
@ -291,24 +293,26 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin)
low |= IOART_INTALO;
if (intpin->io_masked)
low |= IOART_INTMSET;
switch (intpin->io_vector) {
case VECTOR_EXTINT:
switch (intpin->io_irq) {
case IRQ_EXTINT:
KASSERT(intpin->io_edgetrigger,
("ExtINT not edge triggered"));
low |= IOART_DELEXINT;
break;
case VECTOR_NMI:
case IRQ_NMI:
KASSERT(intpin->io_edgetrigger,
("NMI not edge triggered"));
low |= IOART_DELNMI;
break;
case VECTOR_SMI:
case IRQ_SMI:
KASSERT(intpin->io_edgetrigger,
("SMI not edge triggered"));
low |= IOART_DELSMI;
break;
default:
low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector);
KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
intpin->io_irq));
low |= IOART_DELLOPRI | intpin->io_vector;
}
/* Write the values to the APIC. */
@ -334,7 +338,7 @@ ioapic_program_destination(struct ioapic_intsrc *intpin)
if (bootverbose) {
printf("ioapic%u: routing intpin %u (", io->io_id,
intpin->io_intpin);
ioapic_print_vector(intpin);
ioapic_print_irq(intpin);
printf(") to cluster %u\n", intpin->io_dest);
}
ioapic_program_intpin(intpin);
@ -365,10 +369,27 @@ static void
ioapic_enable_intr(struct intsrc *isrc)
{
struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
struct ioapic *io = (struct ioapic *)isrc->is_pic;
if (intpin->io_dest == DEST_NONE) {
/*
* Allocate an APIC vector for this interrupt pin. Once
* we have a vector we program the interrupt pin. Note
* that after we have booted ioapic_assign_cluster()
* will program the interrupt pin again, but it doesn't
* hurt to do that and trying to avoid that adds needless
* complication.
*/
intpin->io_vector = apic_alloc_vector(intpin->io_irq);
if (bootverbose) {
printf("ioapic%u: routing intpin %u (", io->io_id,
intpin->io_intpin);
ioapic_print_irq(intpin);
printf(") to vector %u\n", intpin->io_vector);
}
ioapic_program_intpin(intpin);
ioapic_assign_cluster(intpin);
lapic_enable_intr(intpin->io_vector);
apic_enable_vector(intpin->io_vector);
}
}
@ -378,7 +399,7 @@ ioapic_vector(struct intsrc *isrc)
struct ioapic_intsrc *pin;
pin = (struct ioapic_intsrc *)isrc;
return (pin->io_vector);
return (pin->io_irq);
}
static int
@ -386,6 +407,8 @@ ioapic_source_pending(struct intsrc *isrc)
{
struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
if (intpin->io_vector == 0)
return 0;
return (lapic_intr_pending(intpin->io_vector));
}
@ -523,16 +546,16 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
intpin->io_intsrc.is_pic = (struct pic *)io;
intpin->io_intpin = i;
intpin->io_vector = intbase + i;
intpin->io_irq = intbase + i;
/*
* Assume that pin 0 on the first I/O APIC is an ExtINT pin.
* Assume that pins 1-15 are ISA interrupts and that all
* other pins are PCI interrupts.
*/
if (intpin->io_vector == 0)
if (intpin->io_irq == 0)
ioapic_set_extint(io, i);
else if (intpin->io_vector < IOAPIC_ISA_INTS) {
else if (intpin->io_irq < IOAPIC_ISA_INTS) {
intpin->io_bus = APIC_BUS_ISA;
intpin->io_activehi = 1;
intpin->io_edgetrigger = 1;
@ -550,9 +573,9 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
* logical IDs to CPU clusters when they are enabled.
*/
intpin->io_dest = DEST_NONE;
if (bootverbose && intpin->io_vector != VECTOR_DISABLED) {
if (bootverbose && intpin->io_irq != IRQ_DISABLED) {
printf("ioapic%u: intpin %d -> ", io->io_id, i);
ioapic_print_vector(intpin);
ioapic_print_irq(intpin);
printf(" (%s, %s)\n", intpin->io_edgetrigger ?
"edge" : "level", intpin->io_activehi ? "high" :
"low");
@ -573,7 +596,7 @@ ioapic_get_vector(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (-1);
return (io->io_pins[pin].io_vector);
return (io->io_pins[pin].io_irq);
}
int
@ -584,9 +607,9 @@ ioapic_disable_pin(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_DISABLED)
if (io->io_pins[pin].io_irq == IRQ_DISABLED)
return (EINVAL);
io->io_pins[pin].io_vector = VECTOR_DISABLED;
io->io_pins[pin].io_irq = IRQ_DISABLED;
if (bootverbose)
printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
return (0);
@ -600,9 +623,9 @@ ioapic_remap_vector(void *cookie, u_int pin, int vector)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr || vector < 0)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_vector = vector;
io->io_pins[pin].io_irq = vector;
if (bootverbose)
printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
vector, pin);
@ -619,7 +642,7 @@ ioapic_set_bus(void *cookie, u_int pin, int bus_type)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = bus_type;
if (bootverbose)
@ -636,12 +659,12 @@ ioapic_set_nmi(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_NMI)
if (io->io_pins[pin].io_irq == IRQ_NMI)
return (0);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_NMI;
io->io_pins[pin].io_irq = IRQ_NMI;
io->io_pins[pin].io_masked = 0;
io->io_pins[pin].io_edgetrigger = 1;
io->io_pins[pin].io_activehi = 1;
@ -659,12 +682,12 @@ ioapic_set_smi(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_SMI)
if (io->io_pins[pin].io_irq == IRQ_SMI)
return (0);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_SMI;
io->io_pins[pin].io_irq = IRQ_SMI;
io->io_pins[pin].io_masked = 0;
io->io_pins[pin].io_edgetrigger = 1;
io->io_pins[pin].io_activehi = 1;
@ -682,12 +705,12 @@ ioapic_set_extint(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_EXTINT)
if (io->io_pins[pin].io_irq == IRQ_EXTINT)
return (0);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_EXTINT;
io->io_pins[pin].io_irq = IRQ_EXTINT;
if (enable_extint)
io->io_pins[pin].io_masked = 0;
else
@ -708,7 +731,7 @@ ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_activehi = (pol == INTR_POLARITY_HIGH);
if (bootverbose)
@ -725,7 +748,7 @@ ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
if (bootverbose)
@ -756,18 +779,11 @@ ioapic_register(void *cookie)
io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
io->io_intbase + io->io_numintr - 1);
bsp_id = PCPU_GET(apic_id);
for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
/*
* Finish initializing the pins by programming the vectors
* and delivery mode.
*/
if (pin->io_vector == VECTOR_DISABLED)
continue;
ioapic_program_intpin(pin);
if (pin->io_vector >= NUM_IO_INTS)
continue;
intr_register_source(&pin->io_intsrc);
}
/* Register valid pins as interrupt sources. */
for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
if (pin->io_irq < NUM_IO_INTS)
intr_register_source(&pin->io_intsrc);
}
/*

122
sys/amd64/amd64/local_apic.c
View File

@ -36,10 +36,14 @@ __FBSDID("$FreeBSD$");
#include "opt_hwpmc_hooks.h"
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/smp.h>
#include <sys/proc.h>
@ -56,6 +60,11 @@ __FBSDID("$FreeBSD$");
#include <machine/smp.h>
#include <machine/specialreg.h>
#ifdef DDB
#include <sys/interrupt.h>
#include <ddb/ddb.h>
#endif
/*
* We can handle up to 60 APICs via our logical cluster IDs, but currently
* the physical IDs on Intel processors up to the Pentium 4 are limited to
@ -73,6 +82,10 @@ CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
#define LAPIC_TIMER_STATHZ_DIVIDER 15
#define LAPIC_TIMER_PROFHZ_DIVIDER 3
/* Magic IRQ values for the timer and syscalls. */
#define IRQ_TIMER (NUM_IO_INTS + 1)
#define IRQ_SYSCALL (NUM_IO_INTS + 2)
/*
* Support for local APICs. Local APICs manage interrupts on each
* individual processor as opposed to I/O APICs which receive interrupts
@ -126,6 +139,9 @@ static inthand_t *ioint_handlers[] = {
IDTVEC(apic_isr7), /* 224 - 255 */
};
/* Include IDT_SYSCALL to make indexing easier. */
static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
static u_int32_t lapic_timer_divisors[] = {
APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
@ -197,12 +213,14 @@ lapic_init(uintptr_t addr)
/* Perform basic initialization of the BSP's local APIC. */
lapic_enable();
ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
/* Set BSP's per-CPU local APIC ID. */
PCPU_SET(apic_id, lapic_id());
/* Local APIC timer interrupt. */
setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
/* XXX: error/thermal interrupts */
}
@ -257,18 +275,6 @@ lapic_dump(const char* str)
lapic->lvt_pcint);
}
void
lapic_enable_intr(u_int irq)
{
u_int vector;
vector = apic_irq_to_idt(irq);
KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
KASSERT(ioint_handlers[vector / 32] != NULL,
("No ISR handler for IRQ %u", irq));
setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
}
void
lapic_setup(void)
{
@ -692,31 +698,103 @@ lapic_timer_enable_intr(void)
lapic->lvt_timer = value;
}
/* Translate between IDT vectors and IRQ vectors. */
/* Request a free IDT vector to be used by the specified IRQ. */
u_int
apic_irq_to_idt(u_int irq)
apic_alloc_vector(u_int irq)
{
u_int vector;
KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
vector = irq + APIC_IO_INTS;
if (vector >= IDT_SYSCALL)
vector++;
return (vector);
/*
* Search for a free vector. Currently we just use a very simple
* algorithm to find the first free vector.
*/
mtx_lock_spin(&icu_lock);
for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
if (ioint_irqs[vector] != 0)
continue;
ioint_irqs[vector] = irq;
mtx_unlock_spin(&icu_lock);
return (vector + APIC_IO_INTS);
}
mtx_unlock_spin(&icu_lock);
panic("Couldn't find an APIC vector for IRQ %u", irq);
}
void
apic_enable_vector(u_int vector)
{
KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
KASSERT(ioint_handlers[vector / 32] != NULL,
("No ISR handler for vector %u", vector));
setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
}
/* Release an APIC vector when it's no longer in use. */
void
apic_free_vector(u_int vector, u_int irq)
{
KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
("Vector %u does not map to an IRQ line", vector));
KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
mtx_lock_spin(&icu_lock);
ioint_irqs[vector - APIC_IO_INTS] = 0;
mtx_unlock_spin(&icu_lock);
}
/* Map an IDT vector (APIC) to an IRQ (interrupt source). */
u_int
apic_idt_to_irq(u_int vector)
{
KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
vector <= APIC_IO_INTS + NUM_IO_INTS,
vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
("Vector %u does not map to an IRQ line", vector));
if (vector > IDT_SYSCALL)
vector--;
return (vector - APIC_IO_INTS);
return (ioint_irqs[vector - APIC_IO_INTS]);
}
#ifdef DDB
/*
* Dump data about APIC IDT vector mappings.
*/
DB_SHOW_COMMAND(apic, db_show_apic)
{
struct intsrc *isrc;
int quit, i, verbose;
u_int irq;
quit = 0;
if (strcmp(modif, "vv") == 0)
verbose = 2;
else if (strcmp(modif, "v") == 0)
verbose = 1;
else
verbose = 0;
db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
irq = ioint_irqs[i];
if (irq != 0 && irq != IRQ_SYSCALL) {
db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
if (irq == IRQ_TIMER)
db_printf("lapic timer\n");
else if (irq < NUM_IO_INTS) {
isrc = intr_lookup_source(irq);
if (isrc == NULL || verbose == 0)
db_printf("IRQ %u\n", irq);
else
db_dump_intr_event(isrc->is_event,
verbose == 2);
} else
db_printf("IRQ %u ???\n", irq);
}
}
}
#endif
/*
* APIC probing support code. This includes code to manage enumerators.
*/

5
sys/amd64/include/apicvar.h
View File

@ -173,7 +173,9 @@ inthand_t
IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
IDTVEC(apic_isr7), IDTVEC(spuriousint), IDTVEC(timerint);
u_int apic_irq_to_idt(u_int irq);
u_int apic_alloc_vector(u_int irq);
void apic_enable_vector(u_int vector);
void apic_free_vector(u_int vector, u_int irq);
u_int apic_idt_to_irq(u_int vector);
void apic_register_enumerator(struct apic_enumerator *enumerator);
void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
@ -192,7 +194,6 @@ int ioapic_set_smi(void *cookie, u_int pin);
void lapic_create(u_int apic_id, int boot_cpu);
void lapic_disable(void);
void lapic_dump(const char *str);
void lapic_enable_intr(u_int vector);
void lapic_eoi(void);
int lapic_id(void);
void lapic_init(uintptr_t addr);

32
sys/amd64/include/intr_machdep.h
View File

@ -31,9 +31,35 @@
#ifdef _KERNEL
/* With I/O APIC's we can have up to 191 interrupts. */
#define NUM_IO_INTS 191
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2)
/*
* The maximum number of I/O interrupts we allow. This number is rather
* arbitrary as it is just the maximum IRQ resource value. The interrupt
* source for a given IRQ maps that I/O interrupt to device interrupt
* source whether it be a pin on an interrupt controller or an MSI interrupt.
* The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
* interrupts allocate IDT vectors on demand. Currently we have 191 IDT
* vectors available for device interrupts. On many systems with I/O APICs,
* a lot of the IRQs are not used, so this number can be much larger than
* 191 and still be safe since only interrupt sources in actual use will
* allocate IDT vectors.
*
* For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow
* for IRQs in the range 0 - 254. When MSI support is added this number
* will likely increase.
*/
#define NUM_IO_INTS 255
/*
* - 1 ??? dummy counter.
* - 2 counters for each I/O interrupt.
* - 1 counter for each CPU for lapic timer.
* - 7 counters for each CPU for IPI counters for SMP.
*/
#ifdef SMP
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
#else
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
#endif
#ifndef LOCORE

152
sys/i386/i386/io_apic.c
View File

@ -55,10 +55,10 @@ __FBSDID("$FreeBSD$");
#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
#define VECTOR_EXTINT 252
#define VECTOR_NMI 253
#define VECTOR_SMI 254
#define VECTOR_DISABLED 255
#define IRQ_EXTINT (NUM_IO_INTS + 1)
#define IRQ_NMI (NUM_IO_INTS + 2)
#define IRQ_SMI (NUM_IO_INTS + 3)
#define IRQ_DISABLED (NUM_IO_INTS + 4)
#define DEST_NONE -1
@ -67,22 +67,18 @@ __FBSDID("$FreeBSD$");
static MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures");
/*
* New interrupt support code..
*
* XXX: we really should have the interrupt cookie passed up from new-bus
* just be a int pin, and not map 1:1 to interrupt vector number but should
* use INTR_TYPE_FOO to set priority bands for device classes and do all the
* magic remapping of intpin to vector in here. For now we just cheat as on
* ia64 and map intpin X to vector NRSVIDT + X. Note that we assume that the
* first IO APIC has ISA interrupts on pins 1-15. Not sure how you are
* really supposed to figure out which IO APIC in a system with multiple IO
* APIC's actually has the ISA interrupts routed to it. As far as interrupt
* pin numbers, we use the ACPI System Interrupt number model where each
* IO APIC has a contiguous chunk of the System Interrupt address space.
* I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
* as laid out in the ACPI System Interrupt number model where each I/O
* APIC has a contiguous chunk of the System Interrupt address space.
* We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
* IRQs behave as PCI IRQs by default. We also assume that the pin for
* IRQ 0 is actually an ExtINT pin. The apic enumerators override the
* configuration of individual pins as indicated by their tables.
*/
struct ioapic_intsrc {
struct intsrc io_intsrc;
u_int io_irq;
u_int io_intpin:8;
u_int io_vector:8;
u_int io_activehi:1;
@ -106,7 +102,7 @@ struct ioapic {
static u_int ioapic_read(volatile ioapic_t *apic, int reg);
static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
static const char *ioapic_bus_string(int bus_type);
static void ioapic_print_vector(struct ioapic_intsrc *intpin);
static void ioapic_print_irq(struct ioapic_intsrc *intpin);
static void ioapic_enable_source(struct intsrc *isrc);
static void ioapic_disable_source(struct intsrc *isrc, int eoi);
static void ioapic_eoi_source(struct intsrc *isrc);
@ -177,25 +173,25 @@ ioapic_bus_string(int bus_type)
}
static void
ioapic_print_vector(struct ioapic_intsrc *intpin)
ioapic_print_irq(struct ioapic_intsrc *intpin)
{
switch (intpin->io_vector) {
case VECTOR_DISABLED:
switch (intpin->io_irq) {
case IRQ_DISABLED:
printf("disabled");
break;
case VECTOR_EXTINT:
case IRQ_EXTINT:
printf("ExtINT");
break;
case VECTOR_NMI:
case IRQ_NMI:
printf("NMI");
break;
case VECTOR_SMI:
case IRQ_SMI:
printf("SMI");
break;
default:
printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
intpin->io_vector);
intpin->io_irq);
}
}
@ -258,14 +254,20 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin)
struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
uint32_t low, high, value;
/* For disabled pins, just ensure that they are masked. */
if (intpin->io_vector == VECTOR_DISABLED) {
/*
* If a pin is completely invalid or if it is valid but hasn't
* been enabled yet, just ensure that the pin is masked.
*/
if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
intpin->io_vector == 0)) {
mtx_lock_spin(&icu_lock);
low = ioapic_read(io->io_addr,
IOAPIC_REDTBL_LO(intpin->io_intpin));
if ((low & IOART_INTMASK) == IOART_INTMCLR)
ioapic_write(io->io_addr,
IOAPIC_REDTBL_LO(intpin->io_intpin),
low | IOART_INTMSET);
mtx_unlock_spin(&icu_lock);
return;
}
@ -290,24 +292,26 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin)
low |= IOART_INTALO;
if (intpin->io_masked)
low |= IOART_INTMSET;
switch (intpin->io_vector) {
case VECTOR_EXTINT:
switch (intpin->io_irq) {
case IRQ_EXTINT:
KASSERT(intpin->io_edgetrigger,
("ExtINT not edge triggered"));
low |= IOART_DELEXINT;
break;
case VECTOR_NMI:
case IRQ_NMI:
KASSERT(intpin->io_edgetrigger,
("NMI not edge triggered"));
low |= IOART_DELNMI;
break;
case VECTOR_SMI:
case IRQ_SMI:
KASSERT(intpin->io_edgetrigger,
("SMI not edge triggered"));
low |= IOART_DELSMI;
break;
default:
low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector);
KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
intpin->io_irq));
low |= IOART_DELLOPRI | intpin->io_vector;
}
/* Write the values to the APIC. */
@ -333,7 +337,7 @@ ioapic_program_destination(struct ioapic_intsrc *intpin)
if (bootverbose) {
printf("ioapic%u: routing intpin %u (", io->io_id,
intpin->io_intpin);
ioapic_print_vector(intpin);
ioapic_print_irq(intpin);
printf(") to cluster %u\n", intpin->io_dest);
}
ioapic_program_intpin(intpin);
@ -364,10 +368,27 @@ static void
ioapic_enable_intr(struct intsrc *isrc)
{
struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
struct ioapic *io = (struct ioapic *)isrc->is_pic;
if (intpin->io_dest == DEST_NONE) {
/*
* Allocate an APIC vector for this interrupt pin. Once
* we have a vector we program the interrupt pin. Note
* that after we have booted ioapic_assign_cluster()
* will program the interrupt pin again, but it doesn't
* hurt to do that and trying to avoid that adds needless
* complication.
*/
intpin->io_vector = apic_alloc_vector(intpin->io_irq);
if (bootverbose) {
printf("ioapic%u: routing intpin %u (", io->io_id,
intpin->io_intpin);
ioapic_print_irq(intpin);
printf(") to vector %u\n", intpin->io_vector);
}
ioapic_program_intpin(intpin);
ioapic_assign_cluster(intpin);
lapic_enable_intr(intpin->io_vector);
apic_enable_vector(intpin->io_vector);
}
}
@ -377,7 +398,7 @@ ioapic_vector(struct intsrc *isrc)
struct ioapic_intsrc *pin;
pin = (struct ioapic_intsrc *)isrc;
return (pin->io_vector);
return (pin->io_irq);
}
static int
@ -385,6 +406,8 @@ ioapic_source_pending(struct intsrc *isrc)
{
struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
if (intpin->io_vector == 0)
return 0;
return (lapic_intr_pending(intpin->io_vector));
}
@ -522,16 +545,16 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
intpin->io_intsrc.is_pic = (struct pic *)io;
intpin->io_intpin = i;
intpin->io_vector = intbase + i;
intpin->io_irq = intbase + i;
/*
* Assume that pin 0 on the first I/O APIC is an ExtINT pin.
* Assume that pins 1-15 are ISA interrupts and that all
* other pins are PCI interrupts.
*/
if (intpin->io_vector == 0)
if (intpin->io_irq == 0)
ioapic_set_extint(io, i);
else if (intpin->io_vector < IOAPIC_ISA_INTS) {
else if (intpin->io_irq < IOAPIC_ISA_INTS) {
intpin->io_bus = APIC_BUS_ISA;
intpin->io_activehi = 1;
intpin->io_edgetrigger = 1;
@ -549,9 +572,9 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
* logical IDs to CPU clusters when they are enabled.
*/
intpin->io_dest = DEST_NONE;
if (bootverbose && intpin->io_vector != VECTOR_DISABLED) {
if (bootverbose && intpin->io_irq != IRQ_DISABLED) {
printf("ioapic%u: intpin %d -> ", io->io_id, i);
ioapic_print_vector(intpin);
ioapic_print_irq(intpin);
printf(" (%s, %s)\n", intpin->io_edgetrigger ?
"edge" : "level", intpin->io_activehi ? "high" :
"low");
@ -572,7 +595,7 @@ ioapic_get_vector(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (-1);
return (io->io_pins[pin].io_vector);
return (io->io_pins[pin].io_irq);
}
int
@ -583,9 +606,9 @@ ioapic_disable_pin(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_DISABLED)
if (io->io_pins[pin].io_irq == IRQ_DISABLED)
return (EINVAL);
io->io_pins[pin].io_vector = VECTOR_DISABLED;
io->io_pins[pin].io_irq = IRQ_DISABLED;
if (bootverbose)
printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
return (0);
@ -599,9 +622,9 @@ ioapic_remap_vector(void *cookie, u_int pin, int vector)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr || vector < 0)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_vector = vector;
io->io_pins[pin].io_irq = vector;
if (bootverbose)
printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
vector, pin);
@ -618,7 +641,7 @@ ioapic_set_bus(void *cookie, u_int pin, int bus_type)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = bus_type;
if (bootverbose)
@ -635,12 +658,12 @@ ioapic_set_nmi(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_NMI)
if (io->io_pins[pin].io_irq == IRQ_NMI)
return (0);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_NMI;
io->io_pins[pin].io_irq = IRQ_NMI;
io->io_pins[pin].io_masked = 0;
io->io_pins[pin].io_edgetrigger = 1;
io->io_pins[pin].io_activehi = 1;
@ -658,12 +681,12 @@ ioapic_set_smi(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_SMI)
if (io->io_pins[pin].io_irq == IRQ_SMI)
return (0);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_SMI;
io->io_pins[pin].io_irq = IRQ_SMI;
io->io_pins[pin].io_masked = 0;
io->io_pins[pin].io_edgetrigger = 1;
io->io_pins[pin].io_activehi = 1;
@ -681,12 +704,12 @@ ioapic_set_extint(void *cookie, u_int pin)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr)
return (EINVAL);
if (io->io_pins[pin].io_vector == VECTOR_EXTINT)
if (io->io_pins[pin].io_irq == IRQ_EXTINT)
return (0);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_EXTINT;
io->io_pins[pin].io_irq = IRQ_EXTINT;
if (enable_extint)
io->io_pins[pin].io_masked = 0;
else
@ -707,7 +730,7 @@ ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_activehi = (pol == INTR_POLARITY_HIGH);
if (bootverbose)
@ -724,7 +747,7 @@ ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
io = (struct ioapic *)cookie;
if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
return (EINVAL);
if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
return (EINVAL);
io->io_pins[pin].io_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
if (bootverbose)
@ -755,18 +778,11 @@ ioapic_register(void *cookie)
io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
io->io_intbase + io->io_numintr - 1);
bsp_id = PCPU_GET(apic_id);
for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
/*
* Finish initializing the pins by programming the vectors
* and delivery mode.
*/
if (pin->io_vector == VECTOR_DISABLED)
continue;
ioapic_program_intpin(pin);
if (pin->io_vector >= NUM_IO_INTS)
continue;
intr_register_source(&pin->io_intsrc);
}
/* Register valid pins as interrupt sources. */
for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
if (pin->io_irq < NUM_IO_INTS)
intr_register_source(&pin->io_intsrc);
}
/*

124
sys/i386/i386/local_apic.c
View File

@ -36,10 +36,14 @@ __FBSDID("$FreeBSD$");
#include "opt_hwpmc_hooks.h"
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/smp.h>
@ -55,6 +59,11 @@ __FBSDID("$FreeBSD$");
#include <machine/smp.h>
#include <machine/specialreg.h>
#ifdef DDB
#include <sys/interrupt.h>
#include <ddb/ddb.h>
#endif
/*
* We can handle up to 60 APICs via our logical cluster IDs, but currently
* the physical IDs on Intel processors up to the Pentium 4 are limited to
@ -72,6 +81,10 @@ CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
#define LAPIC_TIMER_STATHZ_DIVIDER 15
#define LAPIC_TIMER_PROFHZ_DIVIDER 3
/* Magic IRQ values for the timer and syscalls. */
#define IRQ_TIMER (NUM_IO_INTS + 1)
#define IRQ_SYSCALL (NUM_IO_INTS + 2)
/*
* Support for local APICs. Local APICs manage interrupts on each
* individual processor as opposed to I/O APICs which receive interrupts
@ -125,6 +138,9 @@ static inthand_t *ioint_handlers[] = {
IDTVEC(apic_isr7), /* 224 - 255 */
};
/* Include IDT_SYSCALL to make indexing easier. */
static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
static u_int32_t lapic_timer_divisors[] = {
APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
@ -197,6 +213,7 @@ lapic_init(uintptr_t addr)
/* Perform basic initialization of the BSP's local APIC. */
lapic_enable();
ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
/* Set BSP's per-CPU local APIC ID. */
PCPU_SET(apic_id, lapic_id());
@ -204,6 +221,7 @@ lapic_init(uintptr_t addr)
/* Local APIC timer interrupt. */
setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,
GSEL(GCODE_SEL, SEL_KPL));
ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
/* XXX: error/thermal interrupts */
}
@ -258,19 +276,6 @@ lapic_dump(const char* str)
lapic->lvt_pcint);
}
void
lapic_enable_intr(u_int irq)
{
u_int vector;
vector = apic_irq_to_idt(irq);
KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
KASSERT(ioint_handlers[vector / 32] != NULL,
("No ISR handler for IRQ %u", irq));
setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
GSEL(GCODE_SEL, SEL_KPL));
}
void
lapic_setup(void)
{
@ -693,31 +698,104 @@ lapic_timer_enable_intr(void)
lapic->lvt_timer = value;
}
/* Translate between IDT vectors and IRQ vectors. */
/* Request a free IDT vector to be used by the specified IRQ. */
u_int
apic_irq_to_idt(u_int irq)
apic_alloc_vector(u_int irq)
{
u_int vector;
KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
vector = irq + APIC_IO_INTS;
if (vector >= IDT_SYSCALL)
vector++;
return (vector);
/*
* Search for a free vector. Currently we just use a very simple
* algorithm to find the first free vector.
*/
mtx_lock_spin(&icu_lock);
for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
if (ioint_irqs[vector] != 0)
continue;
ioint_irqs[vector] = irq;
mtx_unlock_spin(&icu_lock);
return (vector + APIC_IO_INTS);
}
mtx_unlock_spin(&icu_lock);
panic("Couldn't find an APIC vector for IRQ %u", irq);
}
void
apic_enable_vector(u_int vector)
{
KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
KASSERT(ioint_handlers[vector / 32] != NULL,
("No ISR handler for vector %u", vector));
setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
GSEL(GCODE_SEL, SEL_KPL));
}
/* Release an APIC vector when it's no longer in use. */
void
apic_free_vector(u_int vector, u_int irq)
{
KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
("Vector %u does not map to an IRQ line", vector));
KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
mtx_lock_spin(&icu_lock);
ioint_irqs[vector - APIC_IO_INTS] = 0;
mtx_unlock_spin(&icu_lock);
}
/* Map an IDT vector (APIC) to an IRQ (interrupt source). */
u_int
apic_idt_to_irq(u_int vector)
{
KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
vector <= APIC_IO_INTS + NUM_IO_INTS,
vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
("Vector %u does not map to an IRQ line", vector));
if (vector > IDT_SYSCALL)
vector--;
return (vector - APIC_IO_INTS);
return (ioint_irqs[vector - APIC_IO_INTS]);
}
#ifdef DDB
/*
* Dump data about APIC IDT vector mappings.
*/
DB_SHOW_COMMAND(apic, db_show_apic)
{
struct intsrc *isrc;
int quit, i, verbose;
u_int irq;
quit = 0;
if (strcmp(modif, "vv") == 0)
verbose = 2;
else if (strcmp(modif, "v") == 0)
verbose = 1;
else
verbose = 0;
db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
irq = ioint_irqs[i];
if (irq != 0 && irq != IRQ_SYSCALL) {
db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
if (irq == IRQ_TIMER)
db_printf("lapic timer\n");
else if (irq < NUM_IO_INTS) {
isrc = intr_lookup_source(irq);
if (isrc == NULL || verbose == 0)
db_printf("IRQ %u\n", irq);
else
db_dump_intr_event(isrc->is_event,
verbose == 2);
} else
db_printf("IRQ %u ???\n", irq);
}
}
}
#endif
/*
* APIC probing support code. This includes code to manage enumerators.
*/

5
sys/i386/include/apicvar.h
View File

@ -172,7 +172,9 @@ inthand_t
IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
IDTVEC(apic_isr7), IDTVEC(spuriousint), IDTVEC(timerint);
u_int apic_irq_to_idt(u_int irq);
u_int apic_alloc_vector(u_int irq);
void apic_enable_vector(u_int vector);
void apic_free_vector(u_int vector, u_int irq);
u_int apic_idt_to_irq(u_int vector);
void apic_register_enumerator(struct apic_enumerator *enumerator);
void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
@ -191,7 +193,6 @@ int ioapic_set_smi(void *cookie, u_int pin);
void lapic_create(u_int apic_id, int boot_cpu);
void lapic_disable(void);
void lapic_dump(const char *str);
void lapic_enable_intr(u_int vector);
void lapic_eoi(void);
int lapic_id(void);
void lapic_init(uintptr_t addr);

32
sys/i386/include/intr_machdep.h
View File

@ -31,9 +31,35 @@
#ifdef _KERNEL
/* With I/O APIC's we can have up to 191 interrupts. */
#define NUM_IO_INTS 191
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2)
/*
* The maximum number of I/O interrupts we allow. This number is rather
* arbitrary as it is just the maximum IRQ resource value. The interrupt
* source for a given IRQ maps that I/O interrupt to device interrupt
* source whether it be a pin on an interrupt controller or an MSI interrupt.
* The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
* interrupts allocate IDT vectors on demand. Currently we have 191 IDT
* vectors available for device interrupts. On many systems with I/O APICs,
* a lot of the IRQs are not used, so this number can be much larger than
* 191 and still be safe since only interrupt sources in actual use will
* allocate IDT vectors.
*
* For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow
* for IRQs in the range 0 - 254. When MSI support is added this number
* will likely increase.
*/
#define NUM_IO_INTS 255
/*
* - 1 ??? dummy counter.
* - 2 counters for each I/O interrupt.
* - 1 counter for each CPU for lapic timer.
* - 7 counters for each CPU for IPI counters for SMP.
*/
#ifdef SMP
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
#else
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
#endif
#ifndef LOCORE