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Finally bring it support for the i80219 XScale processor.

Browse Source 
Submitted by:	Max M. Boyarov <m.boyarov bsd by>
This commit is contained in:
Olivier Houchard 2006-08-24 23:51:28 +00:00
parent ba282be9f3
commit 11d1528ce0
20 changed files with 899 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
sys/arm/arm/cpufunc.c
View File

@ -71,7 +71,7 @@ __FBSDID("$FreeBSD$");
#include <arm/xscale/i80200/i80200var.h> #include <arm/xscale/i80200/i80200var.h>
#endif #endif
#ifdef CPU_XSCALE_80321 #if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
#include <arm/xscale/i80321/i80321reg.h> #include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h> #include <arm/xscale/i80321/i80321var.h>
#endif #endif
@ -81,7 +81,8 @@ __FBSDID("$FreeBSD$");
#include <arm/xscale/ixp425/ixp425var.h> #include <arm/xscale/ixp425/ixp425var.h>
#endif #endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80219)
#include <arm/xscale/xscalereg.h> #include <arm/xscale/xscalereg.h>
#endif #endif
@ -511,7 +512,9 @@ struct cpu_functions ixp12x0_cpufuncs = {
#endif /* CPU_IXP12X0 */ #endif /* CPU_IXP12X0 */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
struct cpu_functions xscale_cpufuncs = { struct cpu_functions xscale_cpufuncs = {
/* CPU functions */ /* CPU functions */
@ -567,7 +570,8 @@ struct cpu_functions xscale_cpufuncs = {
xscale_setup /* cpu setup */ xscale_setup /* cpu setup */
}; };
#endif #endif
/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
/* /*
* Global constants also used by locore.s * Global constants also used by locore.s
@ -578,9 +582,11 @@ u_int cputype;
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
defined (CPU_ARM10) || \ defined (CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
static void get_cachetype_cp15(void); static void get_cachetype_cp15(void);
/* Additional cache information local to this file. Log2 of some of the /* Additional cache information local to this file. Log2 of some of the
@ -888,9 +894,10 @@ set_cpufuncs()
return 0; return 0;
} }
#endif /* CPU_XSCALE_80200 */ #endif /* CPU_XSCALE_80200 */
#ifdef CPU_XSCALE_80321 #if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 || if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 ||
cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0) { cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0 ||
cputype == CPU_ID_80219_400 || cputype == CPU_ID_80219_600) {
/* /*
* Reset the Performance Monitoring Unit to a * Reset the Performance Monitoring Unit to a
@ -915,6 +922,7 @@ set_cpufuncs()
return 0; return 0;
} }
#endif /* CPU_XSCALE_80321 */ #endif /* CPU_XSCALE_80321 */
#ifdef CPU_XSCALE_PXA2X0 #ifdef CPU_XSCALE_PXA2X0
/* ignore core revision to test PXA2xx CPUs */ /* ignore core revision to test PXA2xx CPUs */
if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 || if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA250 ||
@ -1318,9 +1326,10 @@ late_abort_fixup(arg)
*/ */
#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined (CPU_ARM9) || \ #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined (CPU_ARM9) || \
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
#define IGN 0 #define IGN 0
#define OR 1 #define OR 1
@ -1365,7 +1374,7 @@ parse_cpu_options(args, optlist, cpuctrl)
} }
return(cpuctrl); return(cpuctrl);
} }
#endif /* CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 */ #endif /* CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 || XSCALE*/
#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8)
struct cpu_option arm678_options[] = { struct cpu_option arm678_options[] = {
@ -1787,7 +1796,8 @@ ixp12x0_setup(args)
#endif /* CPU_IXP12X0 */ #endif /* CPU_IXP12X0 */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
struct cpu_option xscale_options[] = { struct cpu_option xscale_options[] = {
#ifdef COMPAT_12 #ifdef COMPAT_12
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE }, { "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
@ -1864,4 +1874,5 @@ xscale_setup(args)
__asm __volatile("mcr p15, 0, %0, c1, c0, 1" __asm __volatile("mcr p15, 0, %0, c1, c0, 1"
: : "r" (auxctl)); : : "r" (auxctl));
} }
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */

3
sys/arm/arm/elf_trampoline.c
View File

@ -64,7 +64,8 @@ void __start(void);
defined(CPU_IXP12X0) defined(CPU_IXP12X0)
#define cpu_idcache_wbinv_all sa1_cache_purgeID #define cpu_idcache_wbinv_all sa1_cache_purgeID
#elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
#define cpu_idcache_wbinv_all xscale_cache_purgeID #define cpu_idcache_wbinv_all xscale_cache_purgeID
#endif #endif

6
sys/arm/arm/identcpu.c
View File

@ -229,6 +229,12 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz",
i80321_steppings }, i80321_steppings },
{ CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz",
xscale_steppings },
{ CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz",
xscale_steppings },
{ CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250",
pxa2x0_steppings }, pxa2x0_steppings },
{ CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210",

118
sys/arm/conf/EP80219 Normal file
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@ -0,0 +1,118 @@
# -*- makefile-bsdmake -*- GENERIC -- Generic kernel configuration file for FreeBSD/arm
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
machine arm
ident EP80219
options PHYSADDR=0xa0000000
options KERNPHYSADDR=0xa0200000
options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm
options STARTUP_PAGETABLE_ADDR=0xa0000000
#options ARM32_NEW_VM_LAYOUT
include "../xscale/i80321/std.ep80219"
#To statically compile in device wiring instead of /boot/device.hints
#hints "GENERIC.hints" #Default places to look for devices.
makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
makeoptions CONF_CFLAGS=-mcpu=xscale
options HZ=100
#options DEVICE_POLLING
options SCHED_4BSD #4BSD scheduler
options INET #InterNETworking
#options INET6 #IPv6 communications protocols
options FFS #Berkeley Fast Filesystem
options SOFTUPDATES #Enable FFS soft updates support
options UFS_ACL #Support for access control lists
options UFS_DIRHASH #Improve performance on big directories
options NFSCLIENT #Network Filesystem Client
options NFSSERVER #Network Filesystem Server
options NFS_ROOT #NFS usable as /, requires NFSCLIENT
#options MSDOSFS #MSDOS Filesystem
options CD9660 #ISO 9660 Filesystem
#options PROCFS #Process filesystem (requires PSEUDOFS)
options PSEUDOFS #Pseudo-filesystem framework
options SCSI_DELAY=5000 #Delay (in ms) before probing SCSI
options KTRACE #ktrace(1) support
options SYSVSHM #SYSV-style shared memory
options SYSVMSG #SYSV-style message queues
options SYSVSEM #SYSV-style semaphores
options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
options KBD_INSTALL_CDEV # install a CDEV entry in /dev
options GEOM_GPT # GUID Partition Tables.
options GEOM_MBR # DOS/MBR partitioning
options GEOM_LABEL # Providers labelization.
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=fxp0
options BOOTP_COMPAT
#options PREEMPTION
device genclock
device loop
device ether
device nexus
device mem # Memory and kernel memory devices
#device saarm
device miibus
device fxp
device uart
device pci
device ata
device atadisk # ATA disk drives
device ataraid # ATA RAID drives
device atapicd # ATAPI CDROM drives
device atapifd # ATAPI floppy drives
device atapist # ATAPI tape drives
options ATA_STATIC_ID # Static device numbering
# SCSI Controllers
device pty
device iopwdog # I80321 Watchdog
device dma # I80321 DMA Controller
# Debugging for use in -current
options KDB
options DDB #Enable the kernel debugger
#options INVARIANTS #Enable calls of extra sanity checking
#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS #Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
#options DIAGNOSTIC
# To make an SMP kernel, the next two are needed
#options SMP # Symmetric MultiProcessor Kernel
#options APIC_IO # Symmetric (APIC) I/O
options XSCALE_CACHE_READ_WRITE_ALLOCATE
device md
device random # Entropy device
options ARM_USE_SMALL_ALLOC
# Floppy drives
options INCLUDE_CONFIG_FILE # Include this file in kernel
#options VERBOSE_SYSINIT
options VERBOSE_INIT_ARM
device bpf
#options ROOTDEVNAME=\"ufs:ad4s1a\"

2
sys/arm/include/armreg.h
View File

@ -155,6 +155,8 @@
#define CPU_ID_80321_600 0x69052430 #define CPU_ID_80321_600 0x69052430
#define CPU_ID_80321_400_B0 0x69052c20 #define CPU_ID_80321_400_B0 0x69052c20
#define CPU_ID_80321_600_B0 0x69052c30 #define CPU_ID_80321_600_B0 0x69052c30
#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */
#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */
#define CPU_ID_IXP425_533 0x690541c0 #define CPU_ID_IXP425_533 0x690541c0
#define CPU_ID_IXP425_400 0x690541d0 #define CPU_ID_IXP425_400 0x690541d0
#define CPU_ID_IXP425_266 0x690541f0 #define CPU_ID_IXP425_266 0x690541f0

8
sys/arm/include/cpuconf.h
View File

@ -64,7 +64,7 @@
#define ARM_ARCH_4 0 #define ARM_ARCH_4 0
#endif #endif
#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219) || \
defined(CPU_XSCALE_PXA2X0)) || defined(CPU_ARM10) defined(CPU_XSCALE_PXA2X0)) || defined(CPU_ARM10)
#define ARM_ARCH_5 1 #define ARM_ARCH_5 1
#else #else
@ -112,7 +112,8 @@
#endif #endif
#if(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ #if(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219))
#define ARM_MMU_XSCALE 1 #define ARM_MMU_XSCALE 1
#else #else
#define ARM_MMU_XSCALE 0 #define ARM_MMU_XSCALE 0
@ -130,7 +131,8 @@
* ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
*/ */
#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80219))
#define ARM_XSCALE_PMU 1 #define ARM_XSCALE_PMU 1
#else #else
#define ARM_XSCALE_PMU 0 #define ARM_XSCALE_PMU 0

17
sys/arm/include/cpufunc.h
View File

@ -371,10 +371,11 @@ extern unsigned arm10_dcache_index_inc;
#endif #endif
#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ #if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \
defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
void armv4_tlb_flushID (void); void armv4_tlb_flushID (void);
void armv4_tlb_flushI (void); void armv4_tlb_flushI (void);
void armv4_tlb_flushD (void); void armv4_tlb_flushD (void);
@ -389,8 +390,9 @@ void ixp12x0_context_switch (void);
void ixp12x0_setup (char *string); void ixp12x0_setup (char *string);
#endif #endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
void xscale_cpwait (void); void xscale_cpwait (void);
void xscale_cpu_sleep (int mode); void xscale_cpu_sleep (int mode);
@ -428,7 +430,8 @@ void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
void xscale_context_switch (void); void xscale_context_switch (void);
void xscale_setup (char *string); void xscale_setup (char *string);
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
#define tlb_flush cpu_tlb_flushID #define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb #define setttb cpu_setttb

521
sys/arm/xscale/i80321/ep80219_machdep.c Normal file
View File

@ -0,0 +1,521 @@
/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
/*-
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* machdep.c
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
*
* Created : 17/09/94
*/
#include "opt_msgbuf.h"
#include "opt_ddb.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysproto.h>
#include <sys/signalvar.h>
#include <sys/imgact.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/linker.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <sys/cons.h>
#include <sys/bio.h>
#include <sys/bus.h>
#include <sys/buf.h>
#include <sys/exec.h>
#include <sys/kdb.h>
#include <sys/msgbuf.h>
#include <machine/reg.h>
#include <machine/cpu.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_pager.h>
#include <vm/vm_map.h>
#include <vm/vnode_pager.h>
#include <machine/pmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
#include <machine/machdep.h>
#include <machine/metadata.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <sys/reboot.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/obiovar.h>
#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_IOPXS 1
#define KERNEL_PT_BEFOREKERN 2
#define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */
#define KERNEL_PT_AFKERNEL_NUM 9
/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
/* Define various stack sizes in pages */
#define IRQ_STACK_SIZE 1
#define ABT_STACK_SIZE 1
#ifdef IPKDB
#define UND_STACK_SIZE 2
#else
#define UND_STACK_SIZE 1
#endif
extern u_int data_abort_handler_address;
extern u_int prefetch_abort_handler_address;
extern u_int undefined_handler_address;
struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
extern void *_end;
extern vm_offset_t sa1_cache_clean_addr;
extern int *end;
struct pcpu __pcpu;
struct pcpu *pcpup = &__pcpu;
/* Physical and virtual addresses for some global pages */
vm_paddr_t phys_avail[10];
vm_paddr_t dump_avail[4];
vm_offset_t physical_pages;
vm_offset_t clean_sva, clean_eva;
struct pv_addr systempage;
struct pv_addr msgbufpv;
struct pv_addr irqstack;
struct pv_addr undstack;
struct pv_addr abtstack;
struct pv_addr kernelstack;
struct pv_addr minidataclean;
static struct trapframe proc0_tf;
/* #define IQ80321_OBIO_BASE 0xfe800000UL */
/* #define IQ80321_OBIO_SIZE 0x00100000UL */
/* Static device mappings. */
static const struct pmap_devmap ep80219_devmap[] = {
/*
* Map the on-board devices VA == PA so that we can access them
* with the MMU on or off.
*/
{
IQ80321_OBIO_BASE,
IQ80321_OBIO_BASE,
IQ80321_OBIO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
IQ80321_IOW_VBASE,
VERDE_OUT_XLATE_IO_WIN0_BASE,
VERDE_OUT_XLATE_IO_WIN_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
IQ80321_80321_VBASE,
VERDE_PMMR_BASE,
VERDE_PMMR_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
0,
0,
0,
0,
0,
}
};
#ifdef DDB
extern vm_offset_t ksym_start, ksym_end;
#endif
extern vm_offset_t xscale_cache_clean_addr;
void *
initarm(void *arg, void *arg2)
{
struct pv_addr kernel_l1pt;
int loop;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
#ifdef DDB
vm_offset_t zstart = 0, zend = 0;
#endif
int i = 0;
uint32_t fake_preload[35];
uint32_t memsize, memstart;
i = 0;
set_cpufuncs();
fake_preload[i++] = MODINFO_NAME;
fake_preload[i++] = strlen("elf kernel") + 1;
strcpy((char*)&fake_preload[i++], "elf kernel");
i += 2;
fake_preload[i++] = MODINFO_TYPE;
fake_preload[i++] = strlen("elf kernel") + 1;
strcpy((char*)&fake_preload[i++], "elf kernel");
i += 2;
fake_preload[i++] = MODINFO_ADDR;
fake_preload[i++] = sizeof(vm_offset_t);
fake_preload[i++] = KERNBASE + 0x00200000;
fake_preload[i++] = MODINFO_SIZE;
fake_preload[i++] = sizeof(uint32_t);
fake_preload[i++] = (uint32_t)&end - KERNBASE - 0x00200000;
#ifdef DDB
if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
fake_preload[i++] = sizeof(vm_offset_t);
fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
fake_preload[i++] = sizeof(vm_offset_t);
fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
zend = lastaddr;
zstart = *(uint32_t *)(KERNVIRTADDR + 4);
ksym_start = zstart;
ksym_end = zend;
} else
#endif
lastaddr = (vm_offset_t)&end;
fake_preload[i++] = 0;
fake_preload[i] = 0;
preload_metadata = (void *)fake_preload;
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
#define KERNEL_TEXT_BASE (KERNBASE + 0x00200000)
freemempos = 0xa0200000;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + 0x20000000;
#define alloc_pages(var, np) \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
i++;
}
freemem_pt = freemempos;
freemempos = 0xa0100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
#ifdef ARM_USE_SMALL_ALLOC
freemempos -= PAGE_SIZE;
freemem_pt = trunc_page(freemem_pt);
freemem_after = freemempos - ((freemem_pt - 0xa0100000) /
PAGE_SIZE) * sizeof(struct arm_small_page);
arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
, (void *)0xc0100000, freemem_pt - 0xa0100000, 1);
freemem_after -= ((freemem_after - 0xa0001000) / PAGE_SIZE) *
sizeof(struct arm_small_page);
arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000),
(void *)0xc0001000,
trunc_page(freemem_after) - 0xa0001000, 0);
freemempos = trunc_page(freemem_after);
freemempos -= PAGE_SIZE;
#endif
/*
* Allocate memory for the l1 and l2 page tables. The scheme to avoid
* wasting memory by allocating the l1pt on the first 16k memory was
* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
* this to work (which is supposed to be the case).
*/
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
&kernel_pt_table[KERNEL_PT_IOPXS]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, IQ80321_SDRAM_START, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, IQ80321_SDRAM_START + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, IQ80321_SDRAM_START + 0x200000,
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
#ifdef ARM_USE_SMALL_ALLOC
if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_devmap_bootstrap(l1pagetable, ep80219_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_UND32_MODE,
undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross reloations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_calibrate_delay();
i80321_sdram_bounds(&obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
&memstart, &memsize);
physmem = memsize / PAGE_SIZE;
cninit();
/* Set stack for exception handlers */
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
proc_linkup(&proc0, &ksegrp0, &thread0);
thread0.td_kstack = kernelstack.pv_va;
thread0.td_pcb = (struct pcb *)
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
thread0.td_pcb->pcb_flags = 0;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
/* Enable MMU, I-cache, D-cache, write buffer. */
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
pmap_bootstrap(pmap_curmaxkvaddr,
0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, MSGBUF_SIZE);
mutex_init();
i = 0;
#ifdef ARM_USE_SMALL_ALLOC
phys_avail[i++] = 0xa0000000;
phys_avail[i++] = 0xa0001000; /*
*XXX: Gross hack to get our
* pages in the vm_page_array
. */
#endif
phys_avail[i++] = round_page(virtual_avail - KERNBASE + IQ80321_SDRAM_START);
phys_avail[i++] = trunc_page(0xa0000000 + memsize - 1);
phys_avail[i++] = 0;
phys_avail[i] = 0;
dump_avail[0] = 0xa0000000;
dump_avail[1] = 0xa0000000 + memsize;
dump_avail[2] = 0;
dump_avail[3] = 0;
/* Do basic tuning, hz etc */
init_param1();
init_param2(physmem);
avail_end = 0xa0000000 + memsize - 1;
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}
extern int
machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(pcib);
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
if (bus != busno)
goto no_mapping;
switch (device) {
/* EP80219 PCI */
case 1: /* Ethernet i82555 10/100 */
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(0));
return (ICU_INT_XINT(0));
case 2: /* UART */
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(1));
return (ICU_INT_XINT(1));
case 3:
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(2));
return (ICU_INT_XINT(2));
case 4: /* MINI-PIC_INT */
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(3));
return( ICU_INT_XINT(3));
default:
no_mapping:
printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
}
return (0);
}

12
sys/arm/xscale/i80321/files.ep80219 Normal file
View File

@ -0,0 +1,12 @@
#$FreeBSD$
#
#
# EP80219 Board Specific
#
arm/xscale/i80321/iq80321.c standard
arm/xscale/i80321/ep80219_machdep.c standard
arm/xscale/i80321/obio.c standard
arm/xscale/i80321/obio_space.c standard
arm/xscale/i80321/uart_cpu_i80321.c optional uart
arm/xscale/i80321/uart_bus_i80321.c optional uart
dev/uart/uart_dev_ns8250.c optional uart

13
sys/arm/xscale/i80321/files.i80219 Normal file
View File

@ -0,0 +1,13 @@
#$FreeBSD$
#
# IOP Specific
#
arm/arm/cpufunc_asm_xscale.S standard
arm/arm/irq_dispatch.S standard
arm/xscale/i80321/i80321.c standard
arm/xscale/i80321/i80321_dma.c optional dma
arm/xscale/i80321/i80321_mcu.c standard
arm/xscale/i80321/i80321_pci.c optional pci
arm/xscale/i80321/i80321_space.c standard
arm/xscale/i80321/i80321_timer.c standard
arm/xscale/i80321/i80321_wdog.c optional iopwdog

12
sys/arm/xscale/i80321/i80321_intr.h
View File

@ -73,9 +73,21 @@ i80321_set_intrsteer(void)
: "r" (intr_steer & ICU_INT_HWMASK)); : "r" (intr_steer & ICU_INT_HWMASK));
} }
#if defined ( CPU_XSCALE_80219 )
#define INT_SWMASK \
((1U << ICU_INT_bit26) | \
(1U << ICU_INT_bit25) | \
(1U << ICU_INT_bit23) | \
(1U << ICU_INT_bit22) | \
(1U << ICU_INT_bit7) | \
(1U << ICU_INT_bit6) | \
(1U << ICU_INT_bit5) | \
(1U << ICU_INT_bit4))
#else
#define INT_SWMASK \ #define INT_SWMASK \
((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \ ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \
(1U << ICU_INT_bit5) | (1U << ICU_INT_bit4)) (1U << ICU_INT_bit5) | (1U << ICU_INT_bit4))
#endif
#if 0 #if 0
static __inline void __attribute__((__unused__)) static __inline void __attribute__((__unused__))

72
sys/arm/xscale/i80321/i80321_pci.c
View File

@ -68,20 +68,6 @@ __FBSDID("$FreeBSD$");
#include <dev/pci/pcireg.h> #include <dev/pci/pcireg.h>
extern struct i80321_softc *i80321_softc; extern struct i80321_softc *i80321_softc;
struct i80321_pci_softc {
device_t sc_dev;
bus_space_tag_t sc_st;
bus_space_handle_t sc_atu_sh;
bus_space_tag_t sc_pciio;
bus_space_tag_t sc_pcimem;
int sc_busno;
struct rman sc_mem_rman;
struct rman sc_io_rman;
struct rman sc_irq_rman;
uint32_t sc_mem;
uint32_t sc_io;
};
static int static int
i80321_pci_probe(device_t dev) i80321_pci_probe(device_t dev)
{ {
@ -259,62 +245,6 @@ i80321_pci_write_config(device_t dev, int bus, int slot, int func, int reg,
} }
static int
i80321_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(pcib);
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
if (bus != busno)
goto no_mapping;
switch (device) {
/* IQ31244 PCI */
case 1: /* PCIX-PCIX bridge */
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
return (ICU_INT_XINT(2));
case 2: /* PCI slot */
/* All pins are wired together. */
return (ICU_INT_XINT(3));
case 3: /* i82546 dual Gig-E */
if (pin == 1 || pin == 2)
return (ICU_INT_XINT(0));
goto no_mapping;
/* IQ80321 PCI */
case 4: /* i82544 Gig-E */
case 8: /*
* Apparently you can set the device for the ethernet adapter
* to 8 with a jumper, so handle that as well
*/
if (pin == 1)
return (ICU_INT_XINT(0));
goto no_mapping;
case 6: /* S-PCI-X slot */
if (pin == 1)
return (ICU_INT_XINT(2));
if (pin == 2)
return (ICU_INT_XINT(3));
goto no_mapping;
default:
no_mapping:
printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
}
return (0);
}
static int static int
i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{ {
@ -453,7 +383,7 @@ static device_method_t i80321_pci_methods[] = {
DEVMETHOD(pcib_maxslots, i80321_pci_maxslots), DEVMETHOD(pcib_maxslots, i80321_pci_maxslots),
DEVMETHOD(pcib_read_config, i80321_pci_read_config), DEVMETHOD(pcib_read_config, i80321_pci_read_config),
DEVMETHOD(pcib_write_config, i80321_pci_write_config), DEVMETHOD(pcib_write_config, i80321_pci_write_config),
DEVMETHOD(pcib_route_interrupt, i80321_pci_route_interrupt), DEVMETHOD(pcib_route_interrupt, machdep_pci_route_interrupt),
{0, 0} {0, 0}
}; };

43
sys/arm/xscale/i80321/i80321reg.h
View File

@ -91,14 +91,18 @@
#define VERDE_MCU_BASE 0x0500 #define VERDE_MCU_BASE 0x0500
#define VERDE_MCU_SIZE 0x0100 #define VERDE_MCU_SIZE 0x0100
#if defined(CPU_XSCALE_80321)
#define VERDE_SSP_BASE 0x0600 #define VERDE_SSP_BASE 0x0600
#define VERDE_SSP_SIZE 0x0080 #define VERDE_SSP_SIZE 0x0080
#endif
#define VERDE_PBIU_BASE 0x0680 #define VERDE_PBIU_BASE 0x0680
#define VERDE_PBIU_SIZE 0x0080 #define VERDE_PBIU_SIZE 0x0080
#if defined(CPU_XSCALE_80321)
#define VERDE_AAU_BASE 0x0800 #define VERDE_AAU_BASE 0x0800
#define VERDE_AAU_SIZE 0x0100 #define VERDE_AAU_SIZE 0x0100
#endif
#define VERDE_I2C_BASE 0x1680 #define VERDE_I2C_BASE 0x1680
#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) #define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00)
@ -335,9 +339,23 @@
#define ICU_INT_XINT0 27 /* external interrupts */ #define ICU_INT_XINT0 27 /* external interrupts */
#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) #define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0)
#define ICU_INT_bit26 26 #define ICU_INT_bit26 26
#if defined (CPU_XSCALE_80219)
#define ICU_INT_bit25 25 /* reserved */
#else
/* CPU_XSCALE_80321 */
#define ICU_INT_SSP 25 /* SSP serial port */ #define ICU_INT_SSP 25 /* SSP serial port */
#endif
#define ICU_INT_MUE 24 /* msg unit error */ #define ICU_INT_MUE 24 /* msg unit error */
#if defined (CPU_XSCALE_80219)
#define ICU_INT_bit23 23 /* reserved */
#else
/* CPU_XSCALE_80321 */
#define ICU_INT_AAUE 23 /* AAU error */ #define ICU_INT_AAUE 23 /* AAU error */
#endif
#define ICU_INT_bit22 22 #define ICU_INT_bit22 22
#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ #define ICU_INT_DMA1E 21 /* DMA Ch 1 error */
#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ #define ICU_INT_DMA0E 20 /* DMA Ch 0 error */
@ -353,8 +371,16 @@
#define ICU_INT_TMR1 10 /* timer 1 */ #define ICU_INT_TMR1 10 /* timer 1 */
#define ICU_INT_TMR0 9 /* timer 0 */ #define ICU_INT_TMR0 9 /* timer 0 */
#define ICU_INT_CPPM 8 /* core processor PMU */ #define ICU_INT_CPPM 8 /* core processor PMU */
#if defined(CPU_XSCALE_80219)
#define ICU_INT_bit7 7 /* reserved */
#define ICU_INT_bit6 6 /* reserved */
#else
/* CPU_XSCALE_80321 */
#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ #define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */
#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ #define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */
#endif
#define ICU_INT_bit5 5 #define ICU_INT_bit5 5
#define ICU_INT_bit4 4 #define ICU_INT_bit4 4
#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ #define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */
@ -362,15 +388,30 @@
#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ #define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */
#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ #define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */
#if defined (CPU_XSCALE_80219)
#define ICU_INT_HWMASK (0xffffffff & \
~((1 << ICU_INT_bit26) | \
(1 << ICU_INT_bit25) | \
(1 << ICU_INT_bit23) | \
(1 << ICU_INT_bit22) | \
(1 << ICU_INT_bit7) | \
(1 << ICU_INT_bit6) | \
(1 << ICU_INT_bit5) | \
(1 << ICU_INT_bit4)))
#else
/* CPU_XSCALE_80321 */
#define ICU_INT_HWMASK (0xffffffff & \ #define ICU_INT_HWMASK (0xffffffff & \
~((1 << ICU_INT_bit26) | \ ~((1 << ICU_INT_bit26) | \
(1 << ICU_INT_bit22) | \ (1 << ICU_INT_bit22) | \
(1 << ICU_INT_bit5) | \ (1 << ICU_INT_bit5) | \
(1 << ICU_INT_bit4))) (1 << ICU_INT_bit4)))
#endif
/* /*
* SSP Serial Port * SSP Serial Port
*/ */
#if defined (CPU_XSCALE_80321)
#define SSP_SSCR0 0x00 /* SSC control 0 */ #define SSP_SSCR0 0x00 /* SSC control 0 */
#define SSP_SSCR1 0x04 /* SSC control 1 */ #define SSP_SSCR1 0x04 /* SSC control 1 */
@ -421,6 +462,8 @@
#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ #define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */
#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ #define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */
#endif /* CPU_XSCALE_80321 */
/* /*
* Peripheral Bus Interface Unit * Peripheral Bus Interface Unit
*/ */

18
sys/arm/xscale/i80321/i80321var.h
View File

@ -111,6 +111,22 @@ struct i80321_softc {
struct rman sc_irq_rman; struct rman sc_irq_rman;
}; };
struct i80321_pci_softc {
device_t sc_dev;
bus_space_tag_t sc_st;
bus_space_handle_t sc_atu_sh;
bus_space_tag_t sc_pciio;
bus_space_tag_t sc_pcimem;
int sc_busno;
struct rman sc_mem_rman;
struct rman sc_io_rman;
struct rman sc_irq_rman;
uint32_t sc_mem;
uint32_t sc_io;
};
void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t, void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
vm_paddr_t *, vm_size_t *); vm_paddr_t *, vm_size_t *);
@ -120,5 +136,7 @@ void i80321_calibrate_delay(void);
void i80321_bs_init(bus_space_tag_t, void *); void i80321_bs_init(bus_space_tag_t, void *);
void i80321_io_bs_init(bus_space_tag_t, void *); void i80321_io_bs_init(bus_space_tag_t, void *);
void i80321_mem_bs_init(bus_space_tag_t, void *); void i80321_mem_bs_init(bus_space_tag_t, void *);
extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin);
#endif /* _ARM_XSCALE_I80321VAR_H_ */ #endif /* _ARM_XSCALE_I80321VAR_H_ */

57
sys/arm/xscale/i80321/iq31244_machdep.c
View File

@ -478,3 +478,60 @@ initarm(void *arg, void *arg2)
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb))); sizeof(struct pcb)));
} }
extern int
machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(pcib);
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
if (bus != busno)
goto no_mapping;
switch (device) {
/* IQ31244 PCI */
case 1: /* PCIX-PCIX bridge */
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
return (ICU_INT_XINT(2));
case 2: /* PCI slot */
/* All pins are wired together. */
return (ICU_INT_XINT(3));
case 3: /* i82546 dual Gig-E */
if (pin == 1 || pin == 2)
return (ICU_INT_XINT(0));
goto no_mapping;
/* IQ80321 PCI */
case 4: /* i82544 Gig-E */
case 8: /*
* Apparently you can set the device for the ethernet adapter
* to 8 with a jumper, so handle that as well
*/
if (pin == 1)
return (ICU_INT_XINT(0));
goto no_mapping;
case 6: /* S-PCI-X slot */
if (pin == 1)
return (ICU_INT_XINT(2));
if (pin == 2)
return (ICU_INT_XINT(3));
goto no_mapping;
default:
no_mapping:
printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
}
return (0);
}

37
sys/arm/xscale/i80321/iq80321.c
View File

@ -157,16 +157,34 @@ iq80321_attach(device_t dev)
b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x4); b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x4);
b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x8); b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x8);
b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0xc); b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0xc);
#ifdef VERBOSE_INIT_ARM
printf("i80321: BAR0 = %08x.%08x BAR1 = %08x.%08x\n",
b0l,b0u, b1l, b1u );
#endif
#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
b0l &= PCI_MAPREG_MEM_ADDR_MASK; b0l &= PCI_MAPREG_MEM_ADDR_MASK;
b0u &= PCI_MAPREG_MEM_ADDR_MASK; b0u &= PCI_MAPREG_MEM_ADDR_MASK;
b1l &= PCI_MAPREG_MEM_ADDR_MASK; b1l &= PCI_MAPREG_MEM_ADDR_MASK;
b1u &= PCI_MAPREG_MEM_ADDR_MASK; b1u &= PCI_MAPREG_MEM_ADDR_MASK;
#ifdef VERBOSE_INIT_ARM
printf("i80219: BAR0 = %08x.%08x BAR1 = %08x.%08x\n",
b0l,b0u, b1l, b1u );
#endif
if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0)) if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0))
sc->sc_is_host = 0; sc->sc_is_host = 0;
else else
sc->sc_is_host = 1; sc->sc_is_host = 1;
/* FIXME: i force it's */
#ifdef CPU_XSCALE_80219
sc->sc_is_host = 1;
#endif
i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
/* /*
* We set up the Inbound Windows as follows: * We set up the Inbound Windows as follows:
@ -224,6 +242,21 @@ iq80321_attach(device_t dev)
sc->sc_iwin[3].iwin_base_hi = 0; sc->sc_iwin[3].iwin_base_hi = 0;
sc->sc_iwin[3].iwin_xlate = 0; sc->sc_iwin[3].iwin_xlate = 0;
sc->sc_iwin[3].iwin_size = 0; sc->sc_iwin[3].iwin_size = 0;
#ifdef VERBOSE_INIT_ARM
printf("i80321: Reserve space for private devices (Inbound Window 1) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n",
sc->sc_iwin[1].iwin_base_hi,
sc->sc_iwin[1].iwin_base_lo,
sc->sc_iwin[1].iwin_xlate,
sc->sc_iwin[1].iwin_size
);
printf("i80321: RAM access (Inbound Window 2) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n",
sc->sc_iwin[2].iwin_base_hi,
sc->sc_iwin[2].iwin_base_lo,
sc->sc_iwin[2].iwin_xlate,
sc->sc_iwin[2].iwin_size
);
#endif
/* /*
* We set up the Outbound Windows as follows: * We set up the Outbound Windows as follows:
@ -259,11 +292,15 @@ iq80321_attach(device_t dev)
device_add_child(dev, "obio", 0); device_add_child(dev, "obio", 0);
device_add_child(dev, "itimer", 0); device_add_child(dev, "itimer", 0);
device_add_child(dev, "iopwdog", 0); device_add_child(dev, "iopwdog", 0);
#ifndef CPU_XSCALE_80219
device_add_child(dev, "iqseg", 0); device_add_child(dev, "iqseg", 0);
#endif
device_add_child(dev, "pcib", busno); device_add_child(dev, "pcib", busno);
device_add_child(dev, "i80321_dma", 0); device_add_child(dev, "i80321_dma", 0);
device_add_child(dev, "i80321_dma", 1); device_add_child(dev, "i80321_dma", 1);
#ifndef CPU_XSCALE_80219
device_add_child(dev, "i80321_aau", 0); device_add_child(dev, "i80321_aau", 0);
#endif
bus_generic_probe(dev); bus_generic_probe(dev);
bus_generic_attach(dev); bus_generic_attach(dev);

3
sys/arm/xscale/i80321/iq80321reg.h
View File

@ -85,6 +85,7 @@
#define IQ80321_80321_VBASE (IQ80321_IOW_VBASE + \ #define IQ80321_80321_VBASE (IQ80321_IOW_VBASE + \
VERDE_OUT_XLATE_IO_WIN_SIZE) VERDE_OUT_XLATE_IO_WIN_SIZE)
#define IQ80321_SDRAM_START 0xa0000000
/* /*
* The IQ80321 on-board devices are mapped VA==PA during bootstrap. * The IQ80321 on-board devices are mapped VA==PA during bootstrap.
* Conveniently, the size of the on-board register space is 1 section * Conveniently, the size of the on-board register space is 1 section
@ -95,6 +96,7 @@
#define IQ80321_UART1 0xfe800000UL /* TI 16550 */ #define IQ80321_UART1 0xfe800000UL /* TI 16550 */
#if defined( CPU_XSCALE_80321 )
#define IQ80321_7SEG_MSB 0xfe840000UL #define IQ80321_7SEG_MSB 0xfe840000UL
#define IQ80321_7SEG_LSB 0xfe850000UL #define IQ80321_7SEG_LSB 0xfe850000UL
@ -104,5 +106,6 @@
#define BATTERY_STAT_PRES (1U << 0) #define BATTERY_STAT_PRES (1U << 0)
#define BATTERY_STAT_CHRG (1U << 1) #define BATTERY_STAT_CHRG (1U << 1)
#define BATTERY_STAT_DISCHRG (1U << 2) #define BATTERY_STAT_DISCHRG (1U << 2)
#endif /* CPU_XSCALE_80321 */
#endif /* _IQ80321REG_H_ */ #endif /* _IQ80321REG_H_ */

7
sys/arm/xscale/i80321/std.ep80219 Normal file
View File

@ -0,0 +1,7 @@
#EP80219 board configuration
#$FreeBSD$
include "../xscale/i80321/std.i80219"
files "../xscale/i80321/files.ep80219"
makeoptions KERNPHYSADDR=0xa0200000
makeoptions KERNVIRTADDR=0xc0200000
options COUNTS_PER_SEC=198000000

5
sys/arm/xscale/i80321/std.i80219 Normal file
View File

@ -0,0 +1,5 @@
#XScale i80219 generic configuration
#$FreeBSD$
files "../xscale/i80321/files.i80219"
include "../xscale/std.xscale"
cpu CPU_XSCALE_80219

1
sys/conf/options.arm
View File

@ -9,6 +9,7 @@ CPU_SA1100 opt_global.h
CPU_SA1110 opt_global.h CPU_SA1110 opt_global.h
CPU_ARM9 opt_global.h CPU_ARM9 opt_global.h
CPU_XSCALE_80321 opt_global.h CPU_XSCALE_80321 opt_global.h
CPU_XSCALE_80219 opt_global.h
KERNPHYSADDR opt_global.h KERNPHYSADDR opt_global.h
KERNVIRTADDR opt_global.h KERNVIRTADDR opt_global.h
PHYSADDR opt_global.h PHYSADDR opt_global.h