While accessing EEPROM command register use pre-defined constant
instead of hardcoded value.
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241b812829
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124e2b3fa0
@ -1176,7 +1176,7 @@ re_attach(dev)
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cfg = CSR_READ_1(sc, RL_CFG2);
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cfg = CSR_READ_1(sc, RL_CFG2);
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cfg |= RL_CFG2_MSI;
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cfg |= RL_CFG2_MSI;
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CSR_WRITE_1(sc, RL_CFG2, cfg);
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CSR_WRITE_1(sc, RL_CFG2, cfg);
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CSR_WRITE_1(sc, RL_EECMD, 0);
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CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
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} else
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} else
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pci_release_msi(dev);
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pci_release_msi(dev);
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}
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}
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@ -2933,7 +2933,7 @@ re_setwol(sc)
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CSR_WRITE_1(sc, RL_CFG3, v);
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CSR_WRITE_1(sc, RL_CFG3, v);
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/* Config register write done. */
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/* Config register write done. */
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CSR_WRITE_1(sc, RL_EECMD, 0);
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CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
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v = CSR_READ_1(sc, RL_CFG5);
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v = CSR_READ_1(sc, RL_CFG5);
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v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
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v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
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@ -2980,7 +2980,7 @@ re_clrwol(sc)
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CSR_WRITE_1(sc, RL_CFG3, v);
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CSR_WRITE_1(sc, RL_CFG3, v);
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/* Config register write done. */
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/* Config register write done. */
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CSR_WRITE_1(sc, RL_EECMD, 0);
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CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
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v = CSR_READ_1(sc, RL_CFG5);
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v = CSR_READ_1(sc, RL_CFG5);
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v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
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v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
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