Add more LinuxKPI PCI definitions.
Obtained from: kmacy @ Sponsored by: Mellanox Technologies MFC after: 1 week
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@ -64,8 +64,18 @@ struct pci_device_id {
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#define MODULE_DEVICE_TABLE(bus, table)
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#define PCI_ANY_ID (-1)
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#define PCI_VENDOR_ID_APPLE 0x106b
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#define PCI_VENDOR_ID_ASUSTEK 0x1043
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#define PCI_VENDOR_ID_ATI 0x1002
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#define PCI_VENDOR_ID_DELL 0x1028
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#define PCI_VENDOR_ID_HP 0x103c
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#define PCI_VENDOR_ID_IBM 0x1014
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_VENDOR_ID_MELLANOX 0x15b3
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#define PCI_VENDOR_ID_SERVERWORKS 0x1166
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#define PCI_VENDOR_ID_SONY 0x104d
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#define PCI_VENDOR_ID_TOPSPIN 0x1867
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#define PCI_VENDOR_ID_VIA 0x1106
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#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
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#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46
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#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
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@ -121,6 +131,10 @@ struct pci_device_id {
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#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
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#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
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#define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
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#define PCI_EXP_LNKCAP_CLKPM 0x00040000
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#define PCI_EXP_DEVSTA_TRPND 0x0020
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#define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
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#define IORESOURCE_IO (1 << SYS_RES_IOPORT)
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#define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
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@ -133,9 +147,19 @@ enum pci_bus_speed {
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};
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enum pcie_link_width {
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PCIE_LNK_WIDTH_UNKNOWN = -1,
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PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
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};
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typedef int pci_power_t;
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#define PCI_D0 PCI_POWERSTATE_D0
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#define PCI_D1 PCI_POWERSTATE_D1
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#define PCI_D2 PCI_POWERSTATE_D2
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#define PCI_D3hot PCI_POWERSTATE_D3
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#define PCI_D3cold 4
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#define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
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struct pci_dev;
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struct pci_driver {
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@ -302,6 +326,14 @@ pci_set_master(struct pci_dev *pdev)
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return (0);
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}
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static inline int
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pci_set_power_state(struct pci_dev *pdev, int state)
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{
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pci_set_powerstate(pdev->dev.bsddev, state);
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return (0);
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}
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static inline int
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pci_clear_master(struct pci_dev *pdev)
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{
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@ -368,9 +400,23 @@ pci_disable_msix(struct pci_dev *pdev)
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pci_release_msi(pdev->dev.bsddev);
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}
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static inline bus_addr_t
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pci_bus_address(struct pci_dev *pdev, int bar)
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{
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return (pci_resource_start(pdev, bar));
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}
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#define PCI_CAP_ID_EXP PCIY_EXPRESS
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#define PCI_CAP_ID_PCIX PCIY_PCIX
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#define PCI_CAP_ID_AGP PCIY_AGP
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#define PCI_CAP_ID_PM PCIY_PMG
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#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
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#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
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#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
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#define PCI_EXP_LNKCTL PCIER_LINK_CTL
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#define PCI_EXP_LNKSTA PCIER_LINK_STA
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static inline int
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pci_find_capability(struct pci_dev *pdev, int capid)
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@ -410,7 +456,7 @@ pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)
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*val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
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return (0);
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}
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}
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static inline int
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pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)
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@ -430,7 +476,7 @@ pci_write_config_word(struct pci_dev *pdev, int where, u16 val)
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static inline int
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pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)
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{
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{
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pci_write_config(pdev->dev.bsddev, where, val, 4);
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return (0);
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@ -708,7 +754,8 @@ static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
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}
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}
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static inline int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
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static inline int
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pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
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{
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if (pos & 3)
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return -EINVAL;
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@ -719,7 +766,20 @@ static inline int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *
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return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
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}
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static inline int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
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static inline int
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pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
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{
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if (pos & 3)
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return -EINVAL;
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if (!pcie_capability_reg_implemented(dev, pos))
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return -EINVAL;
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return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
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}
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static inline int
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pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
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{
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if (pos & 1)
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return -EINVAL;
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