- For SAS but neither FC nor SPI controllers default to using MSI (still

allowing their use to be disabled via device hints though). This matches
  what the corresponding Linux driver provided by LSI does. Tested with
  SAS1064.
- There's no need to keep track of the RIDs used.
- Don't allocate MSI/MSI-X as RF_SHAREABLE.
- Remove a comment which no longer applies since r209599.
- Assign NULL rather than 0 to pointers.

MFC after:	1 month
This commit is contained in:
marius 2011-07-13 18:48:51 +00:00
parent 0aa6cb935c
commit 13b1156fcd
2 changed files with 20 additions and 22 deletions

View File

@ -721,11 +721,9 @@ struct mpt_softc {
* DMA Mapping Stuff
*/
struct resource * pci_reg; /* Register map for chip */
int pci_mem_rid; /* Resource ID */
bus_space_tag_t pci_st; /* Bus tag for registers */
bus_space_handle_t pci_sh; /* Bus handle for registers */
/* PIO versions of above. */
int pci_pio_rid;
struct resource * pci_pio_reg;
bus_space_tag_t pci_pio_st;
bus_space_handle_t pci_pio_sh;

View File

@ -362,9 +362,11 @@ mpt_set_options(struct mpt_softc *mpt)
}
tval = 0;
mpt->msi_enable = 0;
if (resource_int_value(device_get_name(mpt->dev),
device_get_unit(mpt->dev), "msi_enable", &tval) == 0 && tval == 1) {
if (mpt->is_sas)
mpt->msi_enable = 1;
if (resource_int_value(device_get_name(mpt->dev),
device_get_unit(mpt->dev), "msi_enable", &tval) == 0) {
mpt->msi_enable = tval;
}
}
#endif
@ -517,9 +519,9 @@ mpt_pci_attach(device_t dev)
* certain reset operations (but must be disabled for
* some cards otherwise).
*/
mpt->pci_pio_rid = PCIR_BAR(mpt_io_bar);
mpt_io_bar = PCIR_BAR(mpt_io_bar);
mpt->pci_pio_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&mpt->pci_pio_rid, RF_ACTIVE);
&mpt_io_bar, RF_ACTIVE);
if (mpt->pci_pio_reg == NULL) {
device_printf(dev, "unable to map registers in PIO mode\n");
goto bad;
@ -528,9 +530,9 @@ mpt_pci_attach(device_t dev)
mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg);
/* Allocate kernel virtual memory for the 9x9's Mem0 region */
mpt->pci_mem_rid = PCIR_BAR(mpt_mem_bar);
mpt_mem_bar = PCIR_BAR(mpt_mem_bar);
mpt->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&mpt->pci_mem_rid, RF_ACTIVE);
&mpt_mem_bar, RF_ACTIVE);
if (mpt->pci_reg == NULL) {
device_printf(dev, "Unable to memory map registers.\n");
if (mpt->is_sas) {
@ -570,7 +572,7 @@ mpt_pci_attach(device_t dev)
}
}
mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd,
RF_ACTIVE | RF_SHAREABLE);
RF_ACTIVE | (mpt->pci_msi_count ? 0 : RF_SHAREABLE));
if (mpt->pci_irq == NULL) {
device_printf(dev, "could not allocate interrupt\n");
goto bad;
@ -589,7 +591,6 @@ mpt_pci_attach(device_t dev)
}
/* Allocate dma memory */
/* XXX JGibbs -Should really be done based on IOCFacts. */
if (mpt_dma_mem_alloc(mpt)) {
mpt_prt(mpt, "Could not allocate DMA memory\n");
goto bad;
@ -655,13 +656,13 @@ mpt_free_bus_resources(struct mpt_softc *mpt)
{
if (mpt->ih) {
bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih);
mpt->ih = 0;
mpt->ih = NULL;
}
if (mpt->pci_irq) {
bus_release_resource(mpt->dev, SYS_RES_IRQ,
mpt->pci_msi_count ? 1 : 0, mpt->pci_irq);
mpt->pci_irq = 0;
rman_get_rid(mpt->pci_irq), mpt->pci_irq);
mpt->pci_irq = NULL;
}
if (mpt->pci_msi_count) {
@ -670,14 +671,14 @@ mpt_free_bus_resources(struct mpt_softc *mpt)
}
if (mpt->pci_pio_reg) {
bus_release_resource(mpt->dev, SYS_RES_IOPORT, mpt->pci_pio_rid,
mpt->pci_pio_reg);
mpt->pci_pio_reg = 0;
bus_release_resource(mpt->dev, SYS_RES_IOPORT,
rman_get_rid(mpt->pci_pio_reg), mpt->pci_pio_reg);
mpt->pci_pio_reg = NULL;
}
if (mpt->pci_reg) {
bus_release_resource(mpt->dev, SYS_RES_MEMORY, mpt->pci_mem_rid,
mpt->pci_reg);
mpt->pci_reg = 0;
bus_release_resource(mpt->dev, SYS_RES_MEMORY,
rman_get_rid(mpt->pci_reg), mpt->pci_reg);
mpt->pci_reg = NULL;
}
MPT_LOCK_DESTROY(mpt);
}
@ -817,10 +818,9 @@ mpt_dma_mem_free(struct mpt_softc *mpt)
bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap);
bus_dma_tag_destroy(mpt->reply_dmat);
bus_dma_tag_destroy(mpt->parent_dmat);
mpt->reply_dmat = 0;
mpt->reply_dmat = NULL;
free(mpt->request_pool, M_DEVBUF);
mpt->request_pool = 0;
mpt->request_pool = NULL;
}
/* Reads modifiable (via PCI transactions) config registers */