FCP-101: Remove fe(4).
Relnotes: yes FCP: https://github.com/freebsd/fcp/blob/master/fcp-0101.md Reviewed by: jhb, imp Differential Revision: https://reviews.freebsd.org/D20230
This commit is contained in:
brooks
parent
88bd52f986
commit
13d57cef27
@ -47,6 +47,7 @@ OLD_FILES+=usr/share/man/man4/ed.4
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OLD_FILES+=usr/share/man/man4/if_ed.4
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OLD_FILES+=usr/share/man/man4/ep.4
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OLD_FILES+=usr/share/man/man4/ex.4
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OLD_FILES+=usr/share/man/man4/fe.4
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# 20190513: libcap_sysctl interface change
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OLD_FILES+=lib/casper/libcap_sysctl.1
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# 20190509: tests/sys/opencrypto requires the net/py-dpkt package.
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@ -8,7 +8,6 @@ MAN= apm.4 \
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CPU_ELAN.4 \
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ctau.4 \
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cx.4 \
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fe.4 \
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glxiic.4 \
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glxsb.4 \
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longrun.4 \
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@ -1,326 +0,0 @@
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.\" All Rights Reserved, Copyright (C) Fujitsu Limited 1995
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.\"
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.\" This document may be used, modified, copied, distributed, and sold, in
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.\" both source and printed form provided that the above copyright, these
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.\" terms and the following disclaimer are retained. The name of the author
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.\" and/or the contributor may not be used to endorse or promote products
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.\" derived from this software without specific prior written permission.
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.\"
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.\" THIS DOCUMENT IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS DOCUMENT, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" Contributed by M. Sekiguchi <seki@sysrap.cs.fujitsu.co.jp>.
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.\" for fe driver.
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.\"
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.\" $FreeBSD$
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.Dd October 24, 2018
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.Dt FE 4 i386
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.Os
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.Sh NAME
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.Nm fe
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.Nd "Fujitsu MB86960A/MB86965A based Ethernet adapters"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following line in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device fe"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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if_fe_load="YES"
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.Ed
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.Pp
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In
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.Pa /boot/device.hints :
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.Cd hint.fe.0.at="isa"
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.Cd hint.fe.0.port="0x300"
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.Cd hint.fe.0.flags="0x0"
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 13.0
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and later.
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See https://github.com/freebsd/fcp/blob/master/fcp-0101.md for more
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information.
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.Sh DESCRIPTION
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The
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.Nm
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is a network device driver
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for Ethernet adapters based on Fujitsu MB86960A, MB86965A,
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or other compatible chips.
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.Pp
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The driver provides automatic I/O port address configuration and
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automatic IRQ configuration,
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when used with suitable adapter hardware.
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.Pp
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The driver works with program I/O data transfer technique.
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It gives a fair performance.
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Shared memory is never used, even if the adapter has one.
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.Pp
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It currently works with Fujitsu FMV-180 series for ISA,
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Allied-Telesis AT1700 series and RE2000 series for ISA,
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and Fujitsu MBH10302 PC card.
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.Ss Parameters
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In the
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.Pa /boot/device.hints
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file, two parameters,
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.Ar port
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and
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.Ar irq ,
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must be specified to reflect adapter hardware settings.
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Another parameter
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.Ar flags
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can be specified to provide additional configuration as an option.
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.Pp
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The
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.Ar port
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parameter specifies a base I/O port address of the adapter.
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It must match with the hardware setting of the adapter.
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The
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.Ar port
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may be left unspecified by removing
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.Dl hint.fe.0.port="..."
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from the file.
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In that case, the driver tries to detect the hardware setting
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of the I/O address automatically.
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This feature may not work with some adapter hardware.
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.Pp
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The
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.Ar irq
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parameter specifies an IRQ number used by the adapter.
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It must match the hardware setting of the adapter.
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.Ar Irq
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may be left unspecified by removing
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.Dl hint.fe.0.irq="..."
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from the file.
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in that case, the driver tries to detect
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the hardware setting of the IRQ automatically.
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This feature may not work on some adapters.
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.Pp
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The
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.Ar flags
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is a numeric value which consists of a combination of various device settings.
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The following flags are defined in the current version.
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To specify two or more settings for a device,
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use a numeric sum of each flag value.
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Flag bits not specified below are reserved and must be set to 0.
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Actually, each bit is either just ignored by the driver,
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or tested and used to control undocumented features of the driver.
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Consult the source program for undocumented features.
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.Bl -tag -width 8n
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.It Li 0x007F
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These flag bits are used
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to initialize DLCR6 register of MB86960A/MB86965A chip,
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when the
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.Li 0x0080
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bit of the
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.Ar flags
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is set.
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See below for more about DLCR6 override feature.
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The
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.Li 0x007F
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flag bits must be 0 unless the
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.Li 0x0080
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bit is set,
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to maintain the compatibility with future versions of the driver.
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.It Li 0x0080
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This flag overrides the default setting to the DLCR6 register
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of MB86960A/MB86965A chip by a user supplied value,
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which is taken from the lower 7 bits of the flag value.
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This is a troubleshooting flag and should not be used
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without understanding of the adapter hardware.
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Consult the Fujitsu manual for more information
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on DLCR6 settings.
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.El
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.Sh HARDWARE
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Controllers and cards supported by the
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.Nm
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driver include:
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.Pp
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.Bl -bullet -compact
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.It
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Allied Telesis RE1000, RE1000Plus, ME1500 (110-pin)
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.It
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CONTEC C-NET(98)P2, C-NET (9N)E (110-pin), C-NET(9N)C (ExtCard)
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.It
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CONTEC C-NET(PC)C PC Card Ethernet
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.It
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Eagle Tech NE200T
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.It
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Eiger Labs EPX-10BT
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.It
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Fujitsu FMV-J182, FMV-J182A
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.It
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Fujitsu MB86960A, MB86965A
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.It
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Fujitsu MBH10303, MBH10302 PC Card Ethernet
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.It
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Fujitsu Towa LA501 Ethernet
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.It
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HITACHI HT-4840-11 PC Card Ethernet
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.It
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NextCom J Link NC5310
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.It
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RATOC REX-5588, REX-9822, REX-4886, and REX-R280
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.It
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RATOC REX-9880/9881/9882/9883
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.It
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TDK LAC-98012, LAC-98013, LAC-98025, LAC-9N011 (110-pin)
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.It
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TDK LAK-CD011, LAK-CD021, LAK-CD021A, LAK-CD021BX
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.It
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Ungermann-Bass Access/PC N98C+(PC85152, PC85142), Access/NOTE
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N98(PC86132) (110-pin)
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.El
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.Sh FEATURES SPECIFIC TO HARDWARE MODELS
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The
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.Nm
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driver has some features and limitations
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which depend on adapter hardware models.
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The following is a summary of these dependencies.
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.Ss Fujitsu FMV-180 series adapters
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Both automatic IRQ detection and automatic I/O port address detection
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is available with these adapters.
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.Pp
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Automatic I/O port address detection feature of
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.Nm
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works mostly fine for FMV-180 series.
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It works even if there are two or more FMV-180s in a system.
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However, some combination of other adapters may confuse the driver.
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It is recommended to explicitly specify
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.Ar port
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when you experience some difficulties with hardware probe.
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.Pp
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Automatic IRQ detection feature of
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.Nm
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works reliably for FMV-180 series.
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It is recommended to explicitly specify
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.Ar irq
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always for FMV-180.
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The hardware setting of IRQ is read
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from the configuration EEPROM on the adapter,
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even when the kernel config file specifies an IRQ value.
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The driver will generate a warning message,
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if the IRQ setting specified in
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.Pa /boot/device.hints
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does not match one stored in EEPROM.
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Then, it will use the value specified in the file.
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(This behavior has been changed from the previous releases.)
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.Ss Allied-Telesis AT1700 series and RE2000 series adapters
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Automatic I/O port address detection
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is available with Allied-Telesis AT1700 series and RE2000 series,
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while it is less reliable than FMV-180 series.
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Using the feature with Allied-Telesis adapters
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is not recommended.
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.Pp
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Automatic IRQ detection is also available with some limitation.
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The
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.Nm
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driver
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tries to get IRQ setting from the configuration EEPROM on the board,
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if
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.Ar irq
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is not specified in
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.Pa /boot/device.hints .
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Unfortunately,
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AT1700 series and RE2000 series seems to have two types of models;
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One type allows IRQ selection from 3/4/5/9,
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while the other from 10/11/12/15.
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Identification of the models are not well known.
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Hence, automatic IRQ detection with Allied-Telesis adapters
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may not be reliable.
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Specify an exact IRQ number if any troubles are encountered.
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.Pp
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Differences between AT1700 series and RE2000 series
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or minor models in those series are not recognized.
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.Ss Fujitsu MBH10302 PC card
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The
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.Nm
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driver supports Fujitsu MBH10302 and compatible PC cards.
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It requires the PC card (PCMCIA) support package.
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.Sh SEE ALSO
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.Xr netstat 1 ,
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.Xr ed 4 ,
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.Xr netintro 4 ,
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.Xr ng_ether 4 ,
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.Xr ifconfig 8
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.Sh HISTORY
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The
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.Nm
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driver appeared in
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.Fx 2.0.5 .
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.Sh AUTHORS, COPYRIGHT AND DISCLAIMER
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The
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.Nm
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driver was originally written and contributed by
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.An M. Sekiguchi Aq Mt seki@sysrap.cs.fujitsu.co.jp ,
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following the
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.Nm ed
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driver written by
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.An David Greenman .
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PC card support in
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.Nm
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is written by
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.An Hidetoshi Kimura Aq Mt h-kimura@tokyo.se.fujitsu.co.jp .
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This manual page was written by
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.An M. Sekiguchi .
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.Pp
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.Em "All Rights Reserved, Copyright (C) Fujitsu Limited 1995"
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.Pp
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This document and the associated software may be used, modified,
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copied, distributed, and sold, in both source and binary form provided
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that the above copyright, these terms and the following disclaimer are
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retained.
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The name of the author and/or the contributor may not be
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used to endorse or promote products derived from this document and the
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associated software without specific prior written permission.
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.Pp
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THIS DOCUMENT AND THE ASSOCIATED SOFTWARE IS PROVIDED BY THE AUTHOR
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AND THE CONTRIBUTOR
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.Dq AS IS
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE AUTHOR OR THE
|
||||
CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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DOCUMENT AND THE ASSOCIATED SOFTWARE, EVEN IF ADVISED OF THE
|
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POSSIBILITY OF SUCH DAMAGE.
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.Sh BUGS
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Following are major known bugs:
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.Pp
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Statistics on the number of collisions maintained by the
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.Nm
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driver is not accurate;
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the
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.Fl i
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option of
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.Xr netstat 1
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shows slightly less value than true number of collisions.
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.Pp
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More mbuf clusters are used than expected.
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The packet receive routine has an intended violation
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against the mbuf cluster allocation policy.
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The unnecessarily allocated clusters are freed within short lifetime,
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and it will not affect long term kernel memory usage.
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.Pp
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Although XNS and IPX support is included in the driver,
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it has never been tested and it is expected to have a lot of bugs.
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@ -1937,7 +1937,6 @@ device xmphy # XaQti XMAC II
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# LinkSys LNE100TX, LNE100TX V2.0, Jaton XpressNet, Alfa Inc GFC2204,
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# KNE110TX.
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# em: Intel Pro/1000 Gigabit Ethernet 82542, 82543, 82544 based adapters.
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# fe: Fujitsu MB86960A/MB86965A Ethernet
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# fxp: Intel EtherExpress Pro/100B
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# (hint of prefer_iomap can be done to prefer I/O instead of Mem mapping)
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# gem: Apple GMAC/Sun ERI/Sun GEM
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@ -2040,9 +2039,6 @@ device xmphy # XaQti XMAC II
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# Order for ISA devices is important here
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device fe
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hint.fe.0.at="isa"
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hint.fe.0.port="0x300"
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device sn
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hint.sn.0.at="isa"
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hint.sn.0.port="0x300"
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@ -1703,8 +1703,6 @@ dev/fdt/fdt_static_dtb.S optional fdt fdt_dtb_static \
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dependency "${FDT_DTS_FILE:T:R}.dtb"
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dev/fdt/simplebus.c optional fdt
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dev/fdt/simple_mfd.c optional fdt
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dev/fe/if_fe.c optional fe
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dev/fe/if_fe_pccard.c optional fe pccard
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dev/filemon/filemon.c optional filemon
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dev/firewire/firewire.c optional firewire
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dev/firewire/fwcrom.c optional firewire
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2258
sys/dev/fe/if_fe.c
2258
sys/dev/fe/if_fe.c
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,361 +0,0 @@
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/*-
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* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
|
||||
*
|
||||
* This software may be used, modified, copied, distributed, and sold, in
|
||||
* both source and binary form provided that the above copyright, these
|
||||
* terms and the following disclaimer are retained. The name of the author
|
||||
* and/or the contributor may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION.
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
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||||
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||||
#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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||||
#include <sys/param.h>
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||||
#include <sys/kernel.h>
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||||
#include <sys/socket.h>
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||||
#include <sys/systm.h>
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||||
#include <sys/lock.h>
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||||
#include <sys/module.h>
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||||
#include <sys/mutex.h>
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||||
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||||
#include <sys/bus.h>
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||||
#include <machine/bus.h>
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#include <sys/rman.h>
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||||
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||||
#include <net/ethernet.h>
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||||
#include <net/if.h>
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||||
#include <net/if_var.h>
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||||
#include <net/if_mib.h>
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||||
#include <net/if_media.h>
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||||
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||||
#include <netinet/in.h>
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||||
#include <netinet/if_ether.h>
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||||
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#include <dev/fe/mb86960.h>
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||||
#include <dev/fe/if_fereg.h>
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||||
#include <dev/fe/if_fevar.h>
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||||
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||||
#include <dev/pccard/pccardvar.h>
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||||
#include <dev/pccard/pccard_cis.h>
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||||
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||||
#include "card_if.h"
|
||||
#include "pccarddevs.h"
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||||
|
||||
/*
|
||||
* PC Card (PCMCIA) specific code.
|
||||
*/
|
||||
static int fe_pccard_probe(device_t);
|
||||
static int fe_pccard_attach(device_t);
|
||||
static int fe_pccard_detach(device_t);
|
||||
|
||||
static const struct fe_pccard_product {
|
||||
struct pccard_product mpp_product;
|
||||
int mpp_flags;
|
||||
int mpp_cfe;
|
||||
#define MPP_MBH10302 1
|
||||
#define MPP_ANYFUNC 2
|
||||
#define MPP_SKIP_TO_CFE 4
|
||||
} fe_pccard_products[] = {
|
||||
/* These need to be first */
|
||||
{ PCMCIA_CARD(FUJITSU2, FMV_J181), MPP_MBH10302 },
|
||||
{ PCMCIA_CARD(FUJITSU2, FMV_J182), 0 },
|
||||
{ PCMCIA_CARD(FUJITSU2, FMV_J182A), 0 },
|
||||
{ PCMCIA_CARD(FUJITSU2, ITCFJ182A), 0 },
|
||||
/* These need to be second */
|
||||
{ PCMCIA_CARD(TDK, LAK_CD011), 0 },
|
||||
{ PCMCIA_CARD(TDK, LAK_CD021BX), 0 },
|
||||
{ PCMCIA_CARD(TDK, LAK_CF010), 0 },
|
||||
#if 0 /* XXX 86960-based? */
|
||||
{ PCMCIA_CARD(TDK, LAK_DFL9610), 0 },
|
||||
#endif
|
||||
{ PCMCIA_CARD(CONTEC, CNETPC), MPP_SKIP_TO_CFE, 2 },
|
||||
{ PCMCIA_CARD(FUJITSU, LA501), 0 },
|
||||
{ PCMCIA_CARD(FUJITSU, LA10S), 0 },
|
||||
{ PCMCIA_CARD(FUJITSU, NE200T), MPP_MBH10302 },/* Sold by Eagle */
|
||||
{ PCMCIA_CARD(HITACHI, HT_4840), MPP_MBH10302 | MPP_SKIP_TO_CFE, 10 },
|
||||
{ PCMCIA_CARD(RATOC, REX_R280), 0 },
|
||||
{ PCMCIA_CARD(XIRCOM, CE), MPP_ANYFUNC },
|
||||
{ { NULL } }
|
||||
};
|
||||
|
||||
static int
|
||||
fe_pccard_probe(device_t dev)
|
||||
{
|
||||
int error;
|
||||
uint32_t fcn = PCCARD_FUNCTION_UNSPEC;
|
||||
const struct fe_pccard_product *pp;
|
||||
int i;
|
||||
|
||||
if ((pp = (const struct fe_pccard_product *)pccard_product_lookup(dev,
|
||||
(const struct pccard_product *)fe_pccard_products,
|
||||
sizeof(fe_pccard_products[0]), NULL)) != NULL) {
|
||||
if (pp->mpp_product.pp_name != NULL)
|
||||
device_set_desc(dev, pp->mpp_product.pp_name);
|
||||
if (pp->mpp_flags & MPP_ANYFUNC)
|
||||
return (0);
|
||||
/* Make sure we're a network function */
|
||||
error = pccard_get_function(dev, &fcn);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
if (fcn != PCCARD_FUNCTION_NETWORK)
|
||||
return (ENXIO);
|
||||
if (pp->mpp_flags & MPP_SKIP_TO_CFE) {
|
||||
for (i = pp->mpp_cfe; i < 32; i++) {
|
||||
if (pccard_select_cfe(dev, i) == 0)
|
||||
goto good;
|
||||
}
|
||||
device_printf(dev,
|
||||
"Failed to map CFE %d or higher\n", pp->mpp_cfe);
|
||||
return ENXIO;
|
||||
}
|
||||
good:;
|
||||
return (0);
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static device_method_t fe_pccard_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, fe_pccard_probe),
|
||||
DEVMETHOD(device_attach, fe_pccard_attach),
|
||||
DEVMETHOD(device_detach, fe_pccard_detach),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t fe_pccard_driver = {
|
||||
"fe",
|
||||
fe_pccard_methods,
|
||||
sizeof (struct fe_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(fe, pccard, fe_pccard_driver, fe_devclass, 0, 0);
|
||||
MODULE_DEPEND(fe, pccard, 1, 1, 1);
|
||||
PCCARD_PNP_INFO(fe_pccard_products);
|
||||
|
||||
static int fe_probe_mbh(device_t, const struct fe_pccard_product *);
|
||||
static int fe_probe_tdk(device_t, const struct fe_pccard_product *);
|
||||
|
||||
static int
|
||||
fe_pccard_attach(device_t dev)
|
||||
{
|
||||
struct fe_softc *sc;
|
||||
const struct fe_pccard_product *pp;
|
||||
int error;
|
||||
|
||||
/* Prepare for the device probe process. */
|
||||
sc = device_get_softc(dev);
|
||||
sc->sc_unit = device_get_unit(dev);
|
||||
|
||||
pp = (const struct fe_pccard_product *) pccard_product_lookup(dev,
|
||||
(const struct pccard_product *)fe_pccard_products,
|
||||
sizeof(fe_pccard_products[0]), NULL);
|
||||
if (pp == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
if (pp->mpp_flags & MPP_MBH10302)
|
||||
error = fe_probe_mbh(dev, pp);
|
||||
else
|
||||
error = fe_probe_tdk(dev, pp);
|
||||
if (error != 0) {
|
||||
fe_release_resource(dev);
|
||||
return (error);
|
||||
}
|
||||
error = fe_alloc_irq(dev, 0);
|
||||
if (error != 0) {
|
||||
fe_release_resource(dev);
|
||||
return (error);
|
||||
}
|
||||
return (fe_attach(dev));
|
||||
}
|
||||
|
||||
/*
|
||||
* feunload - unload the driver and clear the table.
|
||||
*/
|
||||
static int
|
||||
fe_pccard_detach(device_t dev)
|
||||
{
|
||||
struct fe_softc *sc = device_get_softc(dev);
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
|
||||
FE_LOCK(sc);
|
||||
fe_stop(sc);
|
||||
FE_UNLOCK(sc);
|
||||
callout_drain(&sc->timer);
|
||||
ether_ifdetach(ifp);
|
||||
bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
|
||||
if_free(ifp);
|
||||
fe_release_resource(dev);
|
||||
mtx_destroy(&sc->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Probe and initialization for Fujitsu MBH10302 PCMCIA Ethernet interface.
|
||||
* Note that this is for 10302 only; MBH10304 is handled by fe_probe_tdk().
|
||||
*/
|
||||
static void
|
||||
fe_init_mbh(struct fe_softc *sc)
|
||||
{
|
||||
/* Minimal initialization of 86960. */
|
||||
DELAY(200);
|
||||
fe_outb(sc, FE_DLCR6, sc->proto_dlcr6 | FE_D6_DLC_DISABLE);
|
||||
DELAY(200);
|
||||
|
||||
/* Disable all interrupts. */
|
||||
fe_outb(sc, FE_DLCR2, 0);
|
||||
fe_outb(sc, FE_DLCR3, 0);
|
||||
|
||||
/* Enable master interrupt flag. */
|
||||
fe_outb(sc, FE_MBH0, FE_MBH0_MAGIC | FE_MBH0_INTR_ENABLE);
|
||||
}
|
||||
|
||||
static int
|
||||
fe_probe_mbh(device_t dev, const struct fe_pccard_product *pp)
|
||||
{
|
||||
struct fe_softc *sc = device_get_softc(dev);
|
||||
|
||||
static struct fe_simple_probe_struct probe_table [] = {
|
||||
{ FE_DLCR2, 0x58, 0x00 },
|
||||
{ FE_DLCR4, 0x08, 0x00 },
|
||||
{ FE_DLCR6, 0xFF, 0xB6 },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
/* MBH10302 occupies 32 I/O addresses. */
|
||||
if (fe_alloc_port(dev, 32))
|
||||
return ENXIO;
|
||||
|
||||
/* Fill the softc struct with default values. */
|
||||
fe_softc_defaults(sc);
|
||||
|
||||
/*
|
||||
* See if MBH10302 is on its address.
|
||||
* I'm not sure the following probe code works. FIXME.
|
||||
*/
|
||||
if (!fe_simple_probe(sc, probe_table))
|
||||
return ENXIO;
|
||||
|
||||
/* Get our station address from EEPROM. */
|
||||
fe_inblk(sc, FE_MBH10, sc->enaddr, ETHER_ADDR_LEN);
|
||||
|
||||
/* Make sure we got a valid station address. */
|
||||
if (!fe_valid_Ether_p(sc->enaddr, 0))
|
||||
return ENXIO;
|
||||
|
||||
/* Determine the card type. */
|
||||
sc->type = FE_TYPE_MBH;
|
||||
sc->typestr = "MBH10302 (PCMCIA)";
|
||||
|
||||
/* We seems to need our own IDENT bits... FIXME. */
|
||||
sc->proto_dlcr7 = FE_D7_BYTSWP_LH | FE_D7_IDENT_NICE;
|
||||
|
||||
/* Setup hooks. We need a special initialization procedure. */
|
||||
sc->init = fe_init_mbh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
fe_pccard_xircom_mac(const struct pccard_tuple *tuple, void *argp)
|
||||
{
|
||||
uint8_t *enaddr = argp;
|
||||
int i;
|
||||
|
||||
#if 1
|
||||
/*
|
||||
* We fail to map the CIS twice, for reasons unknown. We
|
||||
* may fix this in the future by loading the CIS with a sane
|
||||
* CIS from userland.
|
||||
*/
|
||||
static uint8_t defaultmac[ETHER_ADDR_LEN] = {
|
||||
0x00, 0x80, 0xc7, 0xed, 0x16, 0x7b};
|
||||
|
||||
/* Copy the MAC ADDR and return success */
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
||||
enaddr[i] = defaultmac[i];
|
||||
#else
|
||||
/* FUNCE is not after FUNCID, so we gotta go find it */
|
||||
if (tuple->code != 0x22)
|
||||
return (0);
|
||||
|
||||
/* Make sure this is a sane node */
|
||||
if (tuple->length < ETHER_ADDR_LEN + 3)
|
||||
return (0);
|
||||
|
||||
/* Copy the MAC ADDR and return success */
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
||||
enaddr[i] = pccard_tuple_read_1(tuple, i + 3);
|
||||
#endif
|
||||
return (1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Probe and initialization for TDK/CONTEC PCMCIA Ethernet interface.
|
||||
* by MASUI Kenji <masui@cs.titech.ac.jp>
|
||||
*
|
||||
* (Contec uses TDK Ethernet chip -- hosokawa)
|
||||
*
|
||||
* This version of fe_probe_tdk has been rewrote to handle
|
||||
* *generic* PC Card implementation of Fujitsu MB8696x family. The
|
||||
* name _tdk is just for a historical reason. :-)
|
||||
*/
|
||||
static int
|
||||
fe_probe_tdk (device_t dev, const struct fe_pccard_product *pp)
|
||||
{
|
||||
struct fe_softc *sc = device_get_softc(dev);
|
||||
|
||||
static struct fe_simple_probe_struct probe_table [] = {
|
||||
{ FE_DLCR2, 0x10, 0x00 },
|
||||
{ FE_DLCR4, 0x08, 0x00 },
|
||||
/* { FE_DLCR5, 0x80, 0x00 }, Does not work well. */
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
||||
/* C-NET(PC)C occupies 16 I/O addresses. */
|
||||
if (fe_alloc_port(dev, 16))
|
||||
return ENXIO;
|
||||
|
||||
/* Fill the softc struct with default values. */
|
||||
fe_softc_defaults(sc);
|
||||
|
||||
/*
|
||||
* See if C-NET(PC)C is on its address.
|
||||
*/
|
||||
if (!fe_simple_probe(sc, probe_table))
|
||||
return ENXIO;
|
||||
|
||||
/* Determine the card type. */
|
||||
sc->type = FE_TYPE_TDK;
|
||||
sc->typestr = "Generic MB8696x/78Q837x Ethernet (PCMCIA)";
|
||||
|
||||
pccard_get_ether(dev, sc->enaddr);
|
||||
|
||||
/* Make sure we got a valid station address. */
|
||||
if (!fe_valid_Ether_p(sc->enaddr, 0)) {
|
||||
pccard_cis_scan(dev, fe_pccard_xircom_mac, sc->enaddr);
|
||||
}
|
||||
|
||||
/* Make sure we got a valid station address. */
|
||||
if (!fe_valid_Ether_p(sc->enaddr, 0))
|
||||
return ENXIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,158 +0,0 @@
|
||||
/*-
|
||||
* Hardware specification of various 8696x based Ethernet cards.
|
||||
* Contributed by M. Sekiguchi <seki@sysrap.cs.fujitsu.co.jp>
|
||||
*
|
||||
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
|
||||
*
|
||||
* This software may be used, modified, copied, distributed, and sold,
|
||||
* in both source and binary form provided that the above copyright,
|
||||
* these terms and the following disclaimer are retained. The name of
|
||||
* the author and/or the contributor may not be used to endorse or
|
||||
* promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* Registers on FMV-180 series' ISA bus interface ASIC.
|
||||
* I'm not sure the following register names are appropriate.
|
||||
* Doesn't it look silly, eh? FIXME.
|
||||
*/
|
||||
|
||||
#define FE_FMV0 16 /* Card status register #0 */
|
||||
#define FE_FMV1 17 /* Card status register #1 */
|
||||
#define FE_FMV2 18 /* Card config register #0 */
|
||||
#define FE_FMV3 19 /* Card config register #1 */
|
||||
#define FE_FMV4 20 /* Station address #1 */
|
||||
#define FE_FMV5 21 /* Station address #2 */
|
||||
#define FE_FMV6 22 /* Station address #3 */
|
||||
#define FE_FMV7 23 /* Station address #4 */
|
||||
#define FE_FMV8 24 /* Station address #5 */
|
||||
#define FE_FMV9 25 /* Station address #6 */
|
||||
#define FE_FMV10 26 /* Buffer RAM control register */
|
||||
#define FE_FMV11 27 /* Buffer RAM data register */
|
||||
|
||||
/*
|
||||
* FMV-180 series' ASIC register values.
|
||||
*/
|
||||
|
||||
/* FMV0: Card status register #0: Misc info? */
|
||||
#define FE_FMV0_MEDIA 0x07 /* Supported physical media. */
|
||||
#define FE_FMV0_PRRDY 0x10 /* ??? */
|
||||
#define FE_FMV0_PRERR 0x20 /* ??? */
|
||||
#define FE_FMV0_ERRDY 0x40 /* ??? */
|
||||
#define FE_FMV0_IREQ 0x80 /* ??? */
|
||||
|
||||
#define FE_FMV0_MEDIUM_5 0x01 /* 10base5/Dsub */
|
||||
#define FE_FMV0_MEDIUM_2 0x02 /* 10base2/BNC */
|
||||
#define FE_FMV0_MEDIUM_T 0x04 /* 10baseT/RJ45 */
|
||||
|
||||
/* Card status register #1: Hardware revision. */
|
||||
#define FE_FMV1_REV 0x0F /* Card revision */
|
||||
#define FE_FMV1_UPPER 0xF0 /* Usage unknown */
|
||||
|
||||
/* Card config register #0: I/O port address assignment. */
|
||||
#define FE_FMV2_IOS 0x07 /* I/O selection. */
|
||||
#define FE_FMV2_MES 0x38 /* ??? boot ROM? */
|
||||
#define FE_FMV2_IRS 0xC0 /* IRQ selection. */
|
||||
|
||||
#define FE_FMV2_IOS_SHIFT 0
|
||||
#define FE_FMV2_MES_SHIFT 3
|
||||
#define FE_FMV2_IRS_SHIFT 6
|
||||
|
||||
/* Card config register #1: IRQ enable */
|
||||
#define FE_FMV3_IRQENB 0x80 /* IRQ enable. */
|
||||
|
||||
|
||||
/*
|
||||
* Register(?) specific to AT1700/RE2000.
|
||||
*/
|
||||
|
||||
#define FE_ATI_RESET 0x1F /* Write to reset the 86965. */
|
||||
|
||||
/* EEPROM allocation (offsets) of AT1700/RE2000. */
|
||||
#define FE_ATI_EEP_ADDR 0x08 /* Station address. (8-13) */
|
||||
#define FE_ATI_EEP_MEDIA 0x18 /* Media type. */
|
||||
#define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic. */
|
||||
#define FE_ATI_EEP_MODEL 0x1e /* Hardware type. */
|
||||
#define FE_ATI_EEP_REVISION 0x1f /* Hardware revision. */
|
||||
|
||||
/* Value for FE_ATI_EEP_MODEL. */
|
||||
#define FE_ATI_MODEL_AT1700T 0x00
|
||||
#define FE_ATI_MODEL_AT1700BT 0x01
|
||||
#define FE_ATI_MODEL_AT1700FT 0x02
|
||||
#define FE_ATI_MODEL_AT1700AT 0x03
|
||||
|
||||
|
||||
/*
|
||||
* Registers on MBH10302.
|
||||
*/
|
||||
|
||||
#define FE_MBH0 0x10 /* ??? Including interrupt. */
|
||||
#define FE_MBH1 0x11 /* ??? */
|
||||
#define FE_MBH10 0x1A /* Station address. (10 - 15) */
|
||||
|
||||
/* Values to be set in MBH0 register. */
|
||||
#define FE_MBH0_MAGIC 0x0D /* Just a magic constant? */
|
||||
#define FE_MBH0_INTR 0x10 /* Master interrupt control. */
|
||||
|
||||
#define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts. */
|
||||
#define FE_MBH0_INTR_DISABLE 0x00 /* Disable interrupts. */
|
||||
|
||||
|
||||
/*
|
||||
* Fujitsu MB86965 JLI mode support routines.
|
||||
*/
|
||||
|
||||
/* Datasheet for 86965 explicitly states that it only supports serial
|
||||
* EEPROM with 16 words (32 bytes) capacity. (I.e., 93C06.) However,
|
||||
* ones with 64 words (128 bytes) are available in the marked, namely
|
||||
* 93C46, and are also fully compatible with 86965. It is known that
|
||||
* some boards (e.g., ICL) actually have 93C46 on them and use extra
|
||||
* storage to keep various config info. */
|
||||
#define JLI_EEPROM_SIZE 128
|
||||
|
||||
|
||||
/*
|
||||
* SSi 78Q8377A support routines.
|
||||
*/
|
||||
#define SSI_EEPROM_SIZE 512
|
||||
#define SSI_DIN 0x01
|
||||
#define SSI_DAT 0x01
|
||||
#define SSI_CSL 0x02
|
||||
#define SSI_CLK 0x04
|
||||
#define SSI_EEP 0x10
|
||||
|
||||
#define FE_SSI_EEP_IRQ 9 /* Irq ??? */
|
||||
#define FE_SSI_EEP_ADDR 16 /* Station(MAC) address */
|
||||
#define FE_SSI_EEP_DUPLEX 25 /* Duplex mode ??? */
|
||||
|
||||
|
||||
/*
|
||||
* TDK/LANX boards support routines.
|
||||
*/
|
||||
|
||||
/* AX012/AX013 equips an X24C01 chip, which has 128 bytes of memory cells. */
|
||||
#define LNX_EEPROM_SIZE 128
|
||||
|
||||
/* Bit assignments and command definitions for the serial EEPROM
|
||||
interface register in LANX ASIC. */
|
||||
#define LNX_SDA_HI 0x08 /* Drive SDA line high (logical 1.) */
|
||||
#define LNX_SDA_LO 0x00 /* Drive SDA line low (logical 0.) */
|
||||
#define LNX_SDA_FL 0x08 /* Float (don't drive) SDA line. */
|
||||
#define LNX_SDA_IN 0x01 /* Mask for reading SDA line. */
|
||||
#define LNX_CLK_HI 0x04 /* Drive clock line high (active.) */
|
||||
#define LNX_CLK_LO 0x00 /* Drive clock line low (inactive.) */
|
||||
@ -1,183 +0,0 @@
|
||||
/*-
|
||||
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
|
||||
*
|
||||
* This software may be used, modified, copied, distributed, and sold, in
|
||||
* both source and binary form provided that the above copyright, these
|
||||
* terms and the following disclaimer are retained. The name of the author
|
||||
* and/or the contributor may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION.
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* How many registers does an fe-supported adapter have at maximum? */
|
||||
#define MAXREGISTERS 32
|
||||
|
||||
/* Shouldn't these be defined somewhere else such as isa_device.h? */
|
||||
#define NO_IRQ 0
|
||||
|
||||
/* Flags for stability. */
|
||||
#define UNSTABLE_IRQ 0x01 /* IRQ setting may be incorrect. */
|
||||
#define UNSTABLE_MAC 0x02 /* Probed MAC address may be incorrect. */
|
||||
#define UNSTABLE_TYPE 0x04 /* Probed vendor/model may be incorrect. */
|
||||
|
||||
/* Mapping between media bitmap (in fe_softc.mbitmap) and ifm_media. */
|
||||
#define MB_HA 0x0001
|
||||
#define MB_HM 0x0002
|
||||
#define MB_HT 0x0004
|
||||
#define MB_H2 0x0008
|
||||
#define MB_H5 0x0010
|
||||
#define MB_HF 0x0020
|
||||
#define MB_FT 0x0040
|
||||
|
||||
/* Card types. */
|
||||
#define FE_TYPE_SSI 1
|
||||
#define FE_TYPE_JLI 2
|
||||
#define FE_TYPE_FMV 3
|
||||
#define FE_TYPE_LNX 4
|
||||
#define FE_TYPE_UBN 5
|
||||
#define FE_TYPE_GWY 6
|
||||
#define FE_TYPE_MBH 7
|
||||
#define FE_TYPE_TDK 8
|
||||
#define FE_TYPE_RE1000 9
|
||||
#define FE_TYPE_CNET9NE 10
|
||||
#define FE_TYPE_REX 11
|
||||
|
||||
/*
|
||||
* Data type for a multicast address filter on 8696x.
|
||||
*/
|
||||
struct fe_filter {
|
||||
u_char data [FE_FILTER_LEN];
|
||||
};
|
||||
|
||||
/*
|
||||
* fe_softc: per line info and status
|
||||
*/
|
||||
struct fe_softc {
|
||||
|
||||
/* Used by "common" codes. */
|
||||
struct ifnet *ifp;
|
||||
int sc_unit;
|
||||
u_char enaddr[6];
|
||||
|
||||
/* Used by config codes. */
|
||||
int type;
|
||||
int port_used;
|
||||
struct resource * port_res;
|
||||
struct resource * irq_res;
|
||||
void * irq_handle;
|
||||
|
||||
/* Set by probe() and not modified in later phases. */
|
||||
char const * typestr; /* printable name of the interface. */
|
||||
u_short txb_size; /* size of TX buffer, in bytes */
|
||||
u_char proto_dlcr4; /* DLCR4 prototype. */
|
||||
u_char proto_dlcr5; /* DLCR5 prototype. */
|
||||
u_char proto_dlcr6; /* DLCR6 prototype. */
|
||||
u_char proto_dlcr7; /* DLCR7 prototype. */
|
||||
u_char proto_bmpr13; /* BMPR13 prototype. */
|
||||
u_char stability; /* How stable is this? */
|
||||
u_short priv_info; /* info specific to a vendor/model. */
|
||||
|
||||
/* Vendor/model specific hooks. */
|
||||
void (*init)(struct fe_softc *); /* Just before fe_init(). */
|
||||
void (*stop)(struct fe_softc *); /* Just after fe_stop(). */
|
||||
|
||||
/* Transmission buffer management. */
|
||||
u_short txb_free; /* free bytes in TX buffer */
|
||||
u_char txb_count; /* number of packets in TX buffer */
|
||||
u_char txb_sched; /* number of scheduled packets */
|
||||
|
||||
/* Excessive collision counter (see fe_tint() for details.) */
|
||||
u_char tx_excolls; /* # of excessive collisions. */
|
||||
|
||||
/* Multicast address filter management. */
|
||||
u_char filter_change; /* MARs must be changed ASAP. */
|
||||
struct fe_filter filter;/* new filter value. */
|
||||
|
||||
/* Network management. */
|
||||
struct ifmib_iso_8802_3 mibdata;
|
||||
|
||||
/* Media information. */
|
||||
struct ifmedia media; /* used by if_media. */
|
||||
u_short mbitmap; /* bitmap for supported media; see bit2media */
|
||||
int defmedia; /* default media */
|
||||
void (* msel)(struct fe_softc *); /* media selector. */
|
||||
|
||||
struct mtx lock;
|
||||
struct callout timer;
|
||||
int tx_timeout;
|
||||
};
|
||||
|
||||
struct fe_simple_probe_struct {
|
||||
u_char port; /* Offset from the base I/O address. */
|
||||
u_char mask; /* Bits to be checked. */
|
||||
u_char bits; /* Values to be compared against. */
|
||||
};
|
||||
|
||||
#define FE_LOCK(sc) mtx_lock(&(sc)->lock)
|
||||
#define FE_UNLOCK(sc) mtx_unlock(&(sc)->lock)
|
||||
#define FE_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
|
||||
|
||||
extern devclass_t fe_devclass;
|
||||
|
||||
int fe_attach(device_t);
|
||||
int fe_alloc_port(device_t, int);
|
||||
int fe_alloc_irq(device_t, int);
|
||||
void fe_release_resource(device_t);
|
||||
|
||||
int fe_simple_probe(struct fe_softc const *,
|
||||
struct fe_simple_probe_struct const *);
|
||||
int fe_valid_Ether_p(u_char const *, unsigned);
|
||||
void fe_softc_defaults(struct fe_softc *);
|
||||
void fe_stop(struct fe_softc *sc);
|
||||
void fe_irq_failure(char const *, int, int, char const *);
|
||||
void fe_msel_965(struct fe_softc *);
|
||||
void fe_read_eeprom_jli(struct fe_softc *, u_char *);
|
||||
void fe_init_jli(struct fe_softc *);
|
||||
void fe_read_eeprom_ssi(struct fe_softc *, u_char *);
|
||||
void fe_read_eeprom_lnx(struct fe_softc *, u_char *);
|
||||
void fe_init_lnx(struct fe_softc *);
|
||||
void fe_init_ubn(struct fe_softc *);
|
||||
|
||||
|
||||
#define fe_inb(sc, port) \
|
||||
bus_read_1((sc)->port_res, (port))
|
||||
|
||||
#define fe_outb(sc, port, value) \
|
||||
bus_write_1((sc)->port_res, (port), (value))
|
||||
|
||||
#define fe_inw(sc, port) \
|
||||
bus_read_2((sc)->port_res, (port))
|
||||
|
||||
#define fe_outw(sc, port, value) \
|
||||
bus_write_2((sc)->port_res, (port), (value))
|
||||
|
||||
#define fe_insb(sc, port, addr, count) \
|
||||
bus_read_multi_1((sc)->port_res, (port), (addr), (count))
|
||||
|
||||
#define fe_outsb(sc, port, addr, count) \
|
||||
bus_write_multi_1((sc)->port_res, (port), (addr), (count))
|
||||
|
||||
#define fe_insw(sc, port, addr, count) \
|
||||
bus_read_multi_2((sc)->port_res, (port), (addr), (count))
|
||||
|
||||
#define fe_outsw(sc, port, addr, count) \
|
||||
bus_write_multi_2((sc)->port_res, (port), (addr), (count))
|
||||
|
||||
#define fe_inblk(sc, port, addr, count) \
|
||||
bus_read_region_1((sc)->port_res, (port), (addr), (count))
|
||||
|
||||
#define fe_outblk(sc, port, addr, count) \
|
||||
bus_write_region_1((sc)->port_res, (port), (addr), (count))
|
||||
@ -1,340 +0,0 @@
|
||||
/*-
|
||||
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
|
||||
*
|
||||
* This software may be used, modified, copied, distributed, and sold, in
|
||||
* both source and binary form provided that the above copyright, these
|
||||
* terms and the following disclaimer are retained. The name of the author
|
||||
* and/or the contributor may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Registers of Fujitsu MB86960A/MB86965A series Ethernet controllers.
|
||||
* Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Notes on register naming:
|
||||
*
|
||||
* Fujitsu documents for MB86960A/MB86965A uses no mnemorable names
|
||||
* for their registers. They defined only three names for 32
|
||||
* registers and appended numbers to distinguish registers of
|
||||
* same name. Surprisingly, the numbers represent I/O address
|
||||
* offsets of the registers from the base addresses, and their
|
||||
* names correspond to the "bank" the registers are allocated.
|
||||
* All this means that, for example, to say "read DLCR8" has no more
|
||||
* than to say "read a register at offset 8 on bank DLCR."
|
||||
*
|
||||
* The following definitions may look silly, but that's what Fujitsu
|
||||
* did, and it is necessary to know these names to read Fujitsu
|
||||
* documents..
|
||||
*/
|
||||
|
||||
/* Data Link Control Registers, on invaliant port addresses. */
|
||||
#define FE_DLCR0 0
|
||||
#define FE_DLCR1 1
|
||||
#define FE_DLCR2 2
|
||||
#define FE_DLCR3 3
|
||||
#define FE_DLCR4 4
|
||||
#define FE_DLCR5 5
|
||||
#define FE_DLCR6 6
|
||||
#define FE_DLCR7 7
|
||||
|
||||
/* More DLCRs, on register bank #0. */
|
||||
#define FE_DLCR8 8
|
||||
#define FE_DLCR9 9
|
||||
#define FE_DLCR10 10
|
||||
#define FE_DLCR11 11
|
||||
#define FE_DLCR12 12
|
||||
#define FE_DLCR13 13
|
||||
#define FE_DLCR14 14
|
||||
#define FE_DLCR15 15
|
||||
|
||||
/* Malticast Address Registers. On register bank #1. */
|
||||
#define FE_MAR8 8
|
||||
#define FE_MAR9 9
|
||||
#define FE_MAR10 10
|
||||
#define FE_MAR11 11
|
||||
#define FE_MAR12 12
|
||||
#define FE_MAR13 13
|
||||
#define FE_MAR14 14
|
||||
#define FE_MAR15 15
|
||||
|
||||
/* Buffer Memory Port Registers. On register back #2. */
|
||||
#define FE_BMPR8 8
|
||||
#define FE_BMPR9 9
|
||||
#define FE_BMPR10 10
|
||||
#define FE_BMPR11 11
|
||||
#define FE_BMPR12 12
|
||||
#define FE_BMPR13 13
|
||||
#define FE_BMPR14 14
|
||||
#define FE_BMPR15 15
|
||||
|
||||
/* More BMPRs, only on 86965, accessible only when JLI mode. */
|
||||
#define FE_BMPR16 16
|
||||
#define FE_BMPR17 17
|
||||
#define FE_BMPR18 18
|
||||
#define FE_BMPR19 19
|
||||
|
||||
/*
|
||||
* Definitions of registers.
|
||||
* I don't have Fujitsu documents of MB86960A/MB86965A, so I don't
|
||||
* know the official names for each flags and fields. The following
|
||||
* names are assigned by me (the author of this file,) since I cannot
|
||||
* mnemorize hexadecimal constants for all of these functions.
|
||||
* Comments?
|
||||
*
|
||||
* I've got documents from Fujitsu web site, recently. However, it's
|
||||
* too late. Names for some fields (bits) are kept different from
|
||||
* those used in the Fujitsu documents...
|
||||
*/
|
||||
|
||||
/* DLCR0 -- transmitter status */
|
||||
#define FE_D0_BUSERR 0x01 /* Bus write error? */
|
||||
#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */
|
||||
#define FE_D0_COLLID 0x04 /* Collision on last transmission */
|
||||
#define FE_D0_JABBER 0x08 /* Jabber */
|
||||
#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */
|
||||
#define FE_D0_PKTRCD 0x20 /* Last packet looped back correctly */
|
||||
#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */
|
||||
#define FE_D0_TXDONE 0x80 /* Transmission complete */
|
||||
|
||||
/* DLCR1 -- receiver status */
|
||||
#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */
|
||||
#define FE_D1_CRCERR 0x02 /* CRC error on last packet */
|
||||
#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */
|
||||
#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */
|
||||
#define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */
|
||||
#define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */
|
||||
#define FE_D1_BUSERR 0x40 /* Bus read error */
|
||||
#define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */
|
||||
|
||||
/* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */
|
||||
#define FE_D2_BUSERR FE_D0_BUSERR
|
||||
#define FE_D2_COLL16 FE_D0_COLL16
|
||||
#define FE_D2_COLLID FE_D0_COLLID
|
||||
#define FE_D2_JABBER FE_D0_JABBER
|
||||
#define FE_D2_TXDONE FE_D0_TXDONE
|
||||
|
||||
#define FE_D2_RESERVED 0x70
|
||||
|
||||
/* DLCR3 -- receiver interrupt control; same layout as DLCR1 */
|
||||
#define FE_D3_OVRFLO FE_D1_OVRFLO
|
||||
#define FE_D3_CRCERR FE_D1_CRCERR
|
||||
#define FE_D3_ALGERR FE_D1_ALGERR
|
||||
#define FE_D3_SRTPKT FE_D1_SRTPKT
|
||||
#define FE_D3_RMTRST FE_D1_RMTRST
|
||||
#define FE_D3_DMAEOP FE_D1_DMAEOP
|
||||
#define FE_D3_BUSERR FE_D1_BUSERR
|
||||
#define FE_D3_PKTRDY FE_D1_PKTRDY
|
||||
|
||||
/* DLCR4 -- transmitter operation mode */
|
||||
#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */
|
||||
#define FE_D4_LBC 0x02 /* Loop back test control */
|
||||
#define FE_D4_CNTRL 0x04 /* - tied to CNTRL pin of the chip */
|
||||
#define FE_D4_TEST1 0x08 /* Test output #1 */
|
||||
#define FE_D4_COL 0xF0 /* Collision counter */
|
||||
|
||||
#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */
|
||||
#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */
|
||||
|
||||
#define FE_D4_COL_SHIFT 4
|
||||
|
||||
/* DLCR5 -- receiver operation mode */
|
||||
#define FE_D5_AFM0 0x01 /* Receive packets for other stations */
|
||||
#define FE_D5_AFM1 0x02 /* Receive packets for this station */
|
||||
#define FE_D5_RMTRST 0x04 /* Enable remote reset operation */
|
||||
#define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */
|
||||
#define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */
|
||||
#define FE_D5_BADPKT 0x20 /* Accept packets with error */
|
||||
#define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */
|
||||
#define FE_D5_TEST2 0x80 /* Test output #2 */
|
||||
|
||||
/* DLCR6 -- hardware configuration #0 */
|
||||
#define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */
|
||||
#define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */
|
||||
#define FE_D6_BBW 0x10 /* Buffer SRAM bus width */
|
||||
#define FE_D6_SBW 0x20 /* System bus width */
|
||||
#define FE_D6_SRAM 0x40 /* Buffer SRAM access time */
|
||||
#define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */
|
||||
|
||||
#define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */
|
||||
#define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */
|
||||
#define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */
|
||||
#define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */
|
||||
|
||||
#define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */
|
||||
#define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */
|
||||
#define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */
|
||||
#define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */
|
||||
|
||||
#define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */
|
||||
#define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */
|
||||
|
||||
#define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */
|
||||
#define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */
|
||||
|
||||
#define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */
|
||||
#define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */
|
||||
|
||||
#define FE_D6_DLC_ENABLE 0x00 /* Normal operation */
|
||||
#define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */
|
||||
|
||||
/* DLC7 -- hardware configuration #1 */
|
||||
#define FE_D7_BYTSWP 0x01 /* Host byte order control */
|
||||
#define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */
|
||||
#define FE_D7_RBS 0x0C /* Register bank select */
|
||||
#define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
|
||||
#define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */
|
||||
#define FE_D7_IDENT 0xC0 /* Chip identification */
|
||||
|
||||
#define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */
|
||||
#define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */
|
||||
|
||||
#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */
|
||||
#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */
|
||||
#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */
|
||||
|
||||
#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */
|
||||
#define FE_D7_POWER_UP 0x20 /* Normal operation */
|
||||
|
||||
#define FE_D7_IDENT_TDK 0x00 /* TDK chips? */
|
||||
#define FE_D7_IDENT_NICE 0x80 /* Fujitsu NICE (86960) */
|
||||
#define FE_D7_IDENT_EC 0xC0 /* Fujitsu EtherCoupler (86965) */
|
||||
|
||||
/* DLCR8 thru DLCR13 are for Ethernet station address. */
|
||||
|
||||
/* DLCR14 and DLCR15 are for TDR. (TDR is used for cable diagnostic.) */
|
||||
|
||||
/* MAR8 thru MAR15 are for Multicast address filter. */
|
||||
|
||||
/* BMPR8 and BMPR9 are for packet data. */
|
||||
|
||||
/* BMPR10 -- transmitter start trigger */
|
||||
#define FE_B10_START 0x80 /* Start transmitter */
|
||||
#define FE_B10_COUNT 0x7F /* Packet count */
|
||||
|
||||
/* BMPR11 -- 16 collisions control */
|
||||
#define FE_B11_CTRL 0x01 /* Skip or resend errored packets */
|
||||
#define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */
|
||||
#define FE_B11_MODE2 0x04 /* Automatic restart enable */
|
||||
|
||||
#define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */
|
||||
#define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */
|
||||
|
||||
/* BMPR12 -- DMA enable */
|
||||
#define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */
|
||||
#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */
|
||||
|
||||
/* BMPR13 -- DMA control */
|
||||
#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */
|
||||
#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */
|
||||
#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */
|
||||
#define FE_B13_LNKTST 0x20 /* Link test enable */
|
||||
#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */
|
||||
#define FE_B13_IOUNLK 0x80 /* Change I/O base address, on JLI mode */
|
||||
|
||||
#define FE_B13_BSTCTL_1 0x00
|
||||
#define FE_B13_BSTCTL_4 0x01
|
||||
#define FE_B13_BSTCTL_8 0x02
|
||||
#define FE_B13_BSTCLT_12 0x03
|
||||
|
||||
#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */
|
||||
#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */
|
||||
|
||||
#define FE_B13_PORT_AUTO 0x00 /* Auto detected */
|
||||
#define FE_B13_PORT_TP 0x08 /* Force TP */
|
||||
#define FE_B13_PORT_AUI 0x18 /* Force AUI */
|
||||
|
||||
/* BMPR14 -- More receiver control and more transmission interrupts */
|
||||
#define FE_B14_FILTER 0x01 /* Filter out self-originated packets */
|
||||
#define FE_B14_SQE 0x02 /* SQE interrupt enable */
|
||||
#define FE_B14_SKIP 0x04 /* Skip a received packet */
|
||||
#define FE_B14_RJAB 0x20 /* RJAB interrupt enable */
|
||||
#define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */
|
||||
#define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */
|
||||
|
||||
/* BMPR15 -- More transmitter status; basically same layout as BMPR14 */
|
||||
#define FE_B15_SQE FE_B14_SQE
|
||||
#define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */
|
||||
#define FE_B15_RMTPRT 0x10 /* ??? */
|
||||
#define FE_B15_RAJB FE_B14_RJAB
|
||||
#define FE_B15_LLD FE_B14_LLD
|
||||
#define FE_B15_RLD FE_B14_RLD
|
||||
|
||||
/* BMPR16 -- EEPROM control */
|
||||
#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */
|
||||
#define FE_B16_SELECT 0x20 /* EEPROM chip select */
|
||||
#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */
|
||||
#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */
|
||||
|
||||
/* BMPR17 -- EEPROM data */
|
||||
#define FE_B17_DATA 0x80 /* EEPROM data bit */
|
||||
|
||||
/* BMPR18 -- cycle I/O address setting in JLI mode */
|
||||
|
||||
/* BMPR19 -- ISA interface configuration in JLI mode */
|
||||
#define FE_B19_IRQ 0xC0
|
||||
#define FE_B19_IRQ_SHIFT 6
|
||||
|
||||
#define FE_B19_ROM 0x38
|
||||
#define FE_B19_ROM_SHIFT 3
|
||||
|
||||
#define FE_B19_ADDR 0x07
|
||||
#define FE_B19_ADDR_SHIFT 0
|
||||
|
||||
/*
|
||||
* An extra I/O port address to reset 86965. This location is called
|
||||
* "ID ROM area" by Fujitsu document.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Flags in Receive Packet Header... Basically same layout as DLCR1.
|
||||
*/
|
||||
#define FE_RPH_OVRFLO FE_D1_OVRFLO
|
||||
#define FE_RPH_CRCERR FE_D1_CRCERR
|
||||
#define FE_RPH_ALGERR FE_D1_ALGERR
|
||||
#define FE_RPH_SRTPKT FE_D1_SRTPKT
|
||||
#define FE_RPH_RMTRST FE_D1_RMTRST
|
||||
#define FE_RPH_GOOD 0x20 /* Good packet follows */
|
||||
|
||||
/*
|
||||
* EEPROM specification (of JLI mode).
|
||||
*/
|
||||
|
||||
/* Number of bytes in an EEPROM accessible through 86965. */
|
||||
#define FE_EEPROM_SIZE 32
|
||||
|
||||
/* Offset for JLI config; automatically copied into BMPR19 at startup. */
|
||||
#define FE_EEPROM_CONF 0
|
||||
|
||||
/*
|
||||
* Some 8696x specific constants.
|
||||
*/
|
||||
|
||||
/* Length (in bytes) of a Multicast Address Filter. */
|
||||
#define FE_FILTER_LEN 8
|
||||
|
||||
/* How many packets we can put in the transmission buffer on NIC memory. */
|
||||
#define FE_QUEUEING_MAX 127
|
||||
|
||||
/* Length (in bytes) of a "packet length" word in transmission buffer. */
|
||||
#define FE_DATA_LEN_LEN 2
|
||||
|
||||
/* Special Multicast Address Filter value. */
|
||||
#define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
|
||||
#define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF }
|
||||
@ -271,7 +271,6 @@ device wb # Winbond W89C840F
|
||||
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
|
||||
|
||||
# ISA Ethernet NICs. pccard NICs included.
|
||||
device fe # Fujitsu MB8696x based cards
|
||||
device sn # SMC's 9000 series of Ethernet chips
|
||||
device xe # Xircom pccard Ethernet
|
||||
|
||||
|
||||
@ -118,7 +118,6 @@ SUBDIR= \
|
||||
ext2fs \
|
||||
fdc \
|
||||
fdescfs \
|
||||
${_fe} \
|
||||
${_ffec} \
|
||||
filemon \
|
||||
firewire \
|
||||
@ -599,7 +598,6 @@ _dpms= dpms
|
||||
_em= em
|
||||
_et= et
|
||||
_exca= exca
|
||||
_fe= fe
|
||||
_if_ndis= if_ndis
|
||||
_io= io
|
||||
_ix= ix
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/fe
|
||||
|
||||
KMOD= if_fe
|
||||
SRCS= if_fe.c if_fe_isa.c if_fe_pccard.c
|
||||
|
||||
SRCS+= bus_if.h card_if.h device_if.h isa_if.h pccarddevs.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
Reference in New Issue
Block a user