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Pull in r300429 from upstream llvm trunk (by Benjamin Kramer):

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[X86] Remove special handling for 16 bit for A asm constraints.

  Our 16 bit support is assembler-only + the terrible hack that is
  .code16gcc. Simply using 32 bit registers does the right thing for
  the latter.

  Fixes PR32681.

This fixes some cases of assembling 16 bit code (i.e. SeaBIOS) that uses
the 'A' inline asm constraint, after r316989.

MFC after:	3 days
X-MFC-With:	r316989
This commit is contained in:
Dimitry Andric 2017-04-18 07:02:12 +00:00
parent 64af9561d6
commit 142446e535
2 changed files with 3 additions and 7 deletions
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9
contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -34722,14 +34722,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Subtarget.is64Bit()) {
Res.first = X86::RAX;
Res.second = &X86::GR64_ADRegClass;
} else if (Subtarget.is32Bit()) {
} else {
assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
"Expecting 64, 32 or 16 bit subtarget");
Res.first = X86::EAX;
Res.second = &X86::GR32_ADRegClass;
} else if (Subtarget.is16Bit()) {
Res.first = X86::AX;
Res.second = &X86::GR16_ADRegClass;
} else {
llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
}
return Res;
}

1
contrib/llvm/lib/Target/X86/X86RegisterInfo.td
View File

@ -438,7 +438,6 @@ def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
(add LOW32_ADDR_ACCESS, RBP)>;
// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;