From 1690edb32c826206ec5070376576acd934ab40cf Mon Sep 17 00:00:00 2001
From: Adrian Chadd <adrian@FreeBSD.org>
Date: Thu, 13 Sep 2012 07:17:29 +0000
Subject: [PATCH] Compensate for half/quarter rate differences in MAC clock
 speed.

This fixes the incorrect slot (and likely ACK/RTS timeout) values
which I see when enabling half/quarter rate support on the AR9280.

The resulting math matches the expected calculated default values.
---
 sys/dev/ath/ath_hal/ah.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/sys/dev/ath/ath_hal/ah.c b/sys/dev/ath/ath_hal/ah.c
index 2914193b4bc3..7b533dad1220 100644
--- a/sys/dev/ath/ath_hal/ah.c
+++ b/sys/dev/ath/ath_hal/ah.c
@@ -514,6 +514,13 @@ ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
 			clks <<= 1;
 	} else
 		clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
+
+	/* Compensate for half/quarter rate */
+	if (c != AH_NULL && IEEE80211_IS_CHAN_HALF(c))
+		clks = clks / 2;
+	else if (c != AH_NULL && IEEE80211_IS_CHAN_QUARTER(c))
+		clks = clks / 4;
+
 	return clks;
 }