Convert e500 PCI driver to use common PPC PCI bus glue. No functional
changes.
This commit is contained in:
Nathan Whitehorn
parent
b27a2490bc
commit
178cdf9a39
@ -132,12 +132,12 @@ powerpc/mpc85xx/i2c.c optional iicbus fdt
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powerpc/mpc85xx/isa.c optional mpc85xx isa
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powerpc/mpc85xx/lbc.c optional mpc85xx
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powerpc/mpc85xx/mpc85xx.c optional mpc85xx
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powerpc/mpc85xx/pci_fdt.c optional pci mpc85xx
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powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx
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powerpc/ofw/ofw_cpu.c optional aim
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powerpc/ofw/ofw_machdep.c optional aim
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powerpc/ofw/ofw_pci.c optional pci aim
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powerpc/ofw/ofw_pcibus.c optional pci aim
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powerpc/ofw/ofw_pcib_pci.c optional pci aim
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powerpc/ofw/ofw_pci.c optional pci
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powerpc/ofw/ofw_pcibus.c optional pci
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powerpc/ofw/ofw_pcib_pci.c optional pci
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powerpc/ofw/ofw_real.c optional aim
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powerpc/ofw/ofw_syscons.c optional sc aim
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powerpc/ofw/ofwcall32.S optional aim powerpc
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@ -55,13 +55,15 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <powerpc/ofw/ofw_pci.h>
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#include "ofw_bus_if.h"
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#include "pcib_if.h"
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@ -98,20 +100,15 @@ __FBSDID("$FreeBSD$");
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#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
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struct fsl_pcib_softc {
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struct ofw_pci_softc pci_sc;
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device_t sc_dev;
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struct rman sc_iomem;
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bus_addr_t sc_iomem_va; /* Virtual mapping. */
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bus_addr_t sc_iomem_size;
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bus_addr_t sc_iomem_alloc; /* Next allocation. */
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int sc_iomem_target;
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struct rman sc_ioport;
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bus_addr_t sc_ioport_va; /* Virtual mapping. */
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bus_addr_t sc_ioport_size;
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bus_addr_t sc_ioport_alloc; /* Next allocation. */
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bus_addr_t sc_iomem_alloc, sc_iomem_start, sc_iomem_end;
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int sc_ioport_target;
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bus_addr_t sc_ioport_alloc, sc_ioport_start, sc_ioport_end;
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struct resource *sc_res;
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struct resource *sc_res;
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bus_space_handle_t sc_bsh;
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bus_space_tag_t sc_bst;
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int sc_rid;
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@ -123,8 +120,6 @@ struct fsl_pcib_softc {
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/* Devices that need special attention. */
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int sc_devfn_tundra;
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int sc_devfn_via_ide;
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struct fdt_pci_intr sc_intr_info;
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};
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/* Local forward declerations. */
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@ -137,9 +132,6 @@ static void fsl_pcib_err_init(device_t);
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static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long,
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u_long, u_long);
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static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
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static int fsl_pcib_intr_info(phandle_t, struct fsl_pcib_softc *);
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static int fsl_pcib_set_range(struct fsl_pcib_softc *, int, int, u_long,
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u_long);
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static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long,
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u_long, u_long);
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@ -148,13 +140,6 @@ static int fsl_pcib_attach(device_t);
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static int fsl_pcib_detach(device_t);
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static int fsl_pcib_probe(device_t);
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static struct resource *fsl_pcib_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static int fsl_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
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static int fsl_pcib_release_resource(device_t, device_t, int, int,
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struct resource *);
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static int fsl_pcib_write_ivar(device_t, device_t, int, uintptr_t);
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static int fsl_pcib_maxslots(device_t);
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static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
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@ -173,53 +158,30 @@ static device_method_t fsl_pcib_methods[] = {
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DEVMETHOD(device_attach, fsl_pcib_attach),
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DEVMETHOD(device_detach, fsl_pcib_detach),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, fsl_pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, fsl_pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, fsl_pcib_alloc_resource),
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DEVMETHOD(bus_release_resource, fsl_pcib_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
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DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
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DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
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/* OFW bus interface */
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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DEVMETHOD_END
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};
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static driver_t fsl_pcib_driver = {
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"pcib",
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fsl_pcib_methods,
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sizeof(struct fsl_pcib_softc),
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};
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static devclass_t fsl_pcib_devclass;
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devclass_t pcib_devclass;
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DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, pcib_devclass, 0, 0);
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DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
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sizeof(struct fsl_pcib_softc), ofw_pci_driver);
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DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0);
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static int
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fsl_pcib_probe(device_t dev)
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{
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phandle_t node;
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node = ofw_bus_get_node(dev);
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if (!fdt_is_type(node, "pci"))
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if (ofw_bus_get_type(dev) == NULL ||
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strcmp(ofw_bus_get_type(dev), "pci") != 0)
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return (ENXIO);
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if (!(fdt_is_compatible(node, "fsl,mpc8540-pci") ||
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fdt_is_compatible(node, "fsl,mpc8548-pcie")))
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if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
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ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie")))
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return (ENXIO);
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device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
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@ -232,7 +194,7 @@ fsl_pcib_attach(device_t dev)
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struct fsl_pcib_softc *sc;
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phandle_t node;
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uint32_t cfgreg;
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int maxslot;
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int maxslot, error;
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uint8_t ltssm, capptr;
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sc = device_get_softc(dev);
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@ -273,13 +235,14 @@ fsl_pcib_attach(device_t dev)
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}
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node = ofw_bus_get_node(dev);
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/*
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* Get PCI interrupt info.
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* Initialize generic OF PCI interface (ranges, etc.)
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*/
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if (fsl_pcib_intr_info(node, sc) != 0) {
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device_printf(dev, "could not retrieve interrupt info\n");
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goto err;
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}
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error = ofw_pci_init(dev);
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if (error)
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return (error);
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/*
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* Configure decode windows for PCI(E) access.
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@ -315,11 +278,9 @@ fsl_pcib_attach(device_t dev)
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fsl_pcib_err_init(dev);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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return (ofw_pci_attach(dev));
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err:
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
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return (ENXIO);
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}
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@ -542,37 +503,6 @@ fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
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return (width);
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}
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static u_int
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fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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u_int intpin)
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{
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int err, unit;
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u_int devfn, intline;
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unit = device_get_unit(sc->sc_dev);
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devfn = DEVFN(bus, slot, func);
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if (devfn == sc->sc_devfn_via_ide)
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intline = MAP_IRQ(0, 14);
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else if (devfn == sc->sc_devfn_via_ide + 1)
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intline = MAP_IRQ(0, 10);
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else if (devfn == sc->sc_devfn_via_ide + 2)
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intline = MAP_IRQ(0, 10);
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else {
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if (intpin != 0)
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err = fdt_pci_route_intr(bus, slot, func, intpin,
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&sc->sc_intr_info, &intline);
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else
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intline = 0xff;
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}
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if (bootverbose)
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printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n",
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unit, bus, slot, func, intpin, intline);
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return (intline);
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}
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static int
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fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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{
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@ -583,7 +513,6 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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int bar, maxbar;
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uint16_t vendor, device;
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uint8_t command, hdrtype, class, subclass;
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uint8_t intline, intpin;
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secbus = bus;
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for (slot = 0; slot <= maxslot; slot++) {
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@ -624,13 +553,9 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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bar += fsl_pcib_init_bar(sc, bus, slot, func,
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bar);
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/* Perform interrupt routing. */
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intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_INTPIN, 1);
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intline = fsl_pcib_route_int(sc, bus, slot, func,
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intpin);
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/* Put a placeholder interrupt value */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_INTLINE, intline, 1);
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PCIR_INTLINE, PCI_INVALID_IRQ, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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@ -654,19 +579,19 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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/* Program I/O decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
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PCIR_IOBASEL_1, sc->sc_ioport_start >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
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PCIR_IOLIMITL_1, sc->sc_ioport_end >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
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PCIR_IOBASEH_1, sc->sc_ioport_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
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PCIR_IOLIMITH_1, sc->sc_ioport_end >> 16, 2);
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/* Program (non-prefetchable) memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
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PCIR_MEMBASE_1, sc->sc_iomem_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
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PCIR_MEMLIMIT_1, sc->sc_iomem_end >> 16, 2);
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/* Program prefetchable memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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@ -769,62 +694,6 @@ fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start,
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
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}
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static int
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fsl_pcib_set_range(struct fsl_pcib_softc *sc, int type, int wnd, u_long start,
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u_long size)
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{
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struct rman *rm;
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u_long end, alloc;
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bus_addr_t pci_start, pci_end;
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bus_addr_t *vap, *allocp;
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int error;
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end = start + size - 1;
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switch (type) {
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case SYS_RES_IOPORT:
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rm = &sc->sc_ioport;
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pci_start = 0x0000;
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pci_end = 0xffff;
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alloc = 0x1000;
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vap = &sc->sc_ioport_va;
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allocp = &sc->sc_ioport_alloc;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_iomem;
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pci_start = start;
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pci_end = end;
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alloc = 0;
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vap = &sc->sc_iomem_va;
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allocp = &sc->sc_iomem_alloc;
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break;
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default:
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return (EINVAL);
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}
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rm->rm_type = RMAN_ARRAY;
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rm->rm_start = pci_start;
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rm->rm_end = pci_end;
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error = rman_init(rm);
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if (error)
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return (error);
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error = rman_manage_region(rm, pci_start, pci_end);
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if (error) {
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rman_fini(rm);
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return (error);
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}
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*allocp = pci_start + alloc;
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if (size > 0) {
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*vap = (uintptr_t)pmap_mapdev(start, size);
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fsl_pcib_outbound(sc, wnd, type, start, size, pci_start);
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} else {
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*vap = 0;
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fsl_pcib_outbound(sc, wnd, -1, 0, 0, 0);
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}
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return (0);
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}
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static void
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fsl_pcib_err_init(device_t dev)
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@ -880,106 +749,15 @@ fsl_pcib_detach(device_t dev)
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return (bus_generic_detach(dev));
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}
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static struct resource *
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fsl_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct fsl_pcib_softc *sc = device_get_softc(dev);
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struct rman *rm;
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struct resource *res;
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bus_addr_t va;
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switch (type) {
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case SYS_RES_IOPORT:
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rm = &sc->sc_ioport;
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va = sc->sc_ioport_va;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_iomem;
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va = sc->sc_iomem_va;
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break;
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case SYS_RES_IRQ:
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if (start < 16) {
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device_printf(dev, "%s requested ISA interrupt %lu\n",
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device_get_nameunit(child), start);
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}
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flags |= RF_SHAREABLE;
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return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
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type, rid, start, end, count, flags));
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default:
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return (NULL);
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}
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res = rman_reserve_resource(rm, start, end, count, flags, child);
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if (res == NULL)
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return (NULL);
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rman_set_bustag(res, &bs_le_tag);
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rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start);
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return (res);
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}
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static int
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fsl_pcib_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *res)
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{
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return (rman_release_resource(res));
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}
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static int
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fsl_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct fsl_pcib_softc *sc = device_get_softc(dev);
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switch (which) {
|
||||
case PCIB_IVAR_BUS:
|
||||
*result = sc->sc_busnr;
|
||||
return (0);
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
*result = device_get_unit(dev);
|
||||
return (0);
|
||||
}
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
static int
|
||||
fsl_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
|
||||
{
|
||||
struct fsl_pcib_softc *sc = device_get_softc(dev);
|
||||
|
||||
switch (which) {
|
||||
case PCIB_IVAR_BUS:
|
||||
sc->sc_busnr = value;
|
||||
return (0);
|
||||
}
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
static int
|
||||
fsl_pcib_intr_info(phandle_t node, struct fsl_pcib_softc *sc)
|
||||
{
|
||||
int error;
|
||||
|
||||
if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
|
||||
return (error);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
|
||||
{
|
||||
struct fdt_pci_range io_space, mem_space;
|
||||
device_t dev;
|
||||
int error;
|
||||
int error, i, trgt;
|
||||
|
||||
dev = sc->sc_dev;
|
||||
|
||||
if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
|
||||
device_printf(dev, "could not retrieve 'ranges' data\n");
|
||||
return (error);
|
||||
}
|
||||
fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
|
||||
|
||||
/*
|
||||
* Configure LAW decode windows.
|
||||
@ -990,30 +768,52 @@ fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
|
||||
device_printf(dev, "could not retrieve PCI LAW target info\n");
|
||||
return (error);
|
||||
}
|
||||
error = law_enable(sc->sc_iomem_target, mem_space.base_parent,
|
||||
mem_space.len);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "could not program LAW for PCI MEM range\n");
|
||||
return (error);
|
||||
}
|
||||
error = law_enable(sc->sc_ioport_target, io_space.base_parent,
|
||||
io_space.len);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "could not program LAW for PCI IO range\n");
|
||||
return (error);
|
||||
|
||||
for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
|
||||
switch (sc->pci_sc.sc_range[i].pci_hi &
|
||||
OFW_PCI_PHYS_HI_SPACEMASK) {
|
||||
case OFW_PCI_PHYS_HI_SPACE_CONFIG:
|
||||
continue;
|
||||
case OFW_PCI_PHYS_HI_SPACE_IO:
|
||||
trgt = sc->sc_ioport_target;
|
||||
fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
|
||||
sc->pci_sc.sc_range[i].host,
|
||||
sc->pci_sc.sc_range[i].size,
|
||||
sc->pci_sc.sc_range[i].pci);
|
||||
sc->sc_ioport_start = sc->pci_sc.sc_range[i].host;
|
||||
sc->sc_ioport_end = sc->pci_sc.sc_range[i].host +
|
||||
sc->pci_sc.sc_range[i].size;
|
||||
sc->sc_ioport_alloc = 0x1000 + sc->pci_sc.sc_range[i].pci;
|
||||
break;
|
||||
case OFW_PCI_PHYS_HI_SPACE_MEM32:
|
||||
case OFW_PCI_PHYS_HI_SPACE_MEM64:
|
||||
trgt = sc->sc_iomem_target;
|
||||
fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
|
||||
sc->pci_sc.sc_range[i].host,
|
||||
sc->pci_sc.sc_range[i].size,
|
||||
sc->pci_sc.sc_range[i].pci);
|
||||
sc->sc_iomem_start = sc->pci_sc.sc_range[i].host;
|
||||
sc->sc_iomem_end = sc->pci_sc.sc_range[i].host +
|
||||
sc->pci_sc.sc_range[i].size;
|
||||
sc->sc_iomem_alloc = sc->pci_sc.sc_range[i].pci;
|
||||
break;
|
||||
default:
|
||||
panic("Unknown range type %#x\n",
|
||||
sc->pci_sc.sc_range[i].pci_hi &
|
||||
OFW_PCI_PHYS_HI_SPACEMASK);
|
||||
}
|
||||
error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
|
||||
sc->pci_sc.sc_range[i].size);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "could not program LAW for range "
|
||||
"%d\n", i);
|
||||
return (error);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set outbout and inbound windows.
|
||||
*/
|
||||
fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
|
||||
if ((error = fsl_pcib_set_range(sc, SYS_RES_MEMORY, 1,
|
||||
mem_space.base_parent, mem_space.len)) != 0)
|
||||
return (error);
|
||||
if ((error = fsl_pcib_set_range(sc, SYS_RES_IOPORT, 2,
|
||||
io_space.base_parent, io_space.len)) != 0)
|
||||
return (error);
|
||||
|
||||
fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
|
||||
fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
|
||||
|
||||
@ -1024,3 +824,4 @@ fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user