acpica, pci_host_generic_acpi: redo pci_host_generic_acpi.c
This is a major update for pci_host_generic_acpi.c, the current implementation has some gaps that are better fixed up in one go. The changes are to: * Follow x86 method of not adding PCI resources to PCI host bridge in ACPI code. This has been moved to pci_host_generic_acpi.c, where we walk thru its resources of the host bridge and add them. * Fixup code in pci_host_generic_acpi.c to read all decoded ranges and update the 'ranges' property. This allows us to share most of the code with generic implementation (and the FDT one). * Parse and setup IO ranges and bus ranges when walking the resources above. Drop most of the changes related to this from acpica code. * Add the ECAM memory area as mem resource 0. Implement the logic to get the ECAM area from MCFG (using bus range which we now decode), or from _CBA (using _BBN/bus range). Drop aarch64 ifdefs from acpica code which did part of this. * Switch resource activation to similar code as FDT implementation, this can be moved into generic implementation in a later pass. * Drop the mechanism of using the 7th bit of bus number as the domain, this is not correct and will work only in very specific cases. Use _SEG as PCI domain and use the bus ranges of the host bridge to provide start bus number. This commit should not make any functional change to dev/acpica/acpi.c for other architectures, almost all the changes there are to revert earlier additions in this file done for aarch64. Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D17791
This commit is contained in:
Jayachandran C.
parent
d4d6ad3f05
commit
185c34f7c8
@ -179,9 +179,7 @@ static int acpi_child_location_str_method(device_t acdev, device_t child,
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char *buf, size_t buflen);
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static int acpi_child_pnpinfo_str_method(device_t acdev, device_t child,
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char *buf, size_t buflen);
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#if defined(__i386__) || defined(__amd64__)
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static void acpi_enable_pcie(void);
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#endif
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static void acpi_hint_device_unit(device_t acdev, device_t child,
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const char *name, int *unitp);
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static void acpi_reset_interfaces(device_t dev);
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@ -502,10 +500,8 @@ acpi_attach(device_t dev)
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goto out;
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}
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#if defined(__i386__) || defined(__amd64__)
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/* Handle MCFG table if present. */
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acpi_enable_pcie();
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#endif
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/*
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* Note that some systems (specifically, those with namespace evaluation
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@ -1286,11 +1282,10 @@ acpi_set_resource(device_t dev, device_t child, int type, int rid,
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struct acpi_softc *sc = device_get_softc(dev);
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struct acpi_device *ad = device_get_ivars(child);
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struct resource_list *rl = &ad->ad_rl;
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#if defined(__i386__) || defined(__amd64__)
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ACPI_DEVICE_INFO *devinfo;
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#endif
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rman_res_t end;
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int allow;
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/* Ignore IRQ resources for PCI link devices. */
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if (type == SYS_RES_IRQ &&
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ACPI_ID_PROBE(dev, child, pcilink_ids, NULL) <= 0)
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@ -1305,11 +1300,15 @@ acpi_set_resource(device_t dev, device_t child, int type, int rid,
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* x86 of a PCI bridge claiming the I/O ports used for PCI config
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* access.
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*/
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#if defined(__i386__) || defined(__amd64__)
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if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
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if (ACPI_SUCCESS(AcpiGetObjectInfo(ad->ad_handle, &devinfo))) {
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if ((devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0) {
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if (!(type == SYS_RES_IOPORT && start == CONF1_ADDR_PORT)) {
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#if defined(__i386__) || defined(__amd64__)
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allow = (type == SYS_RES_IOPORT && start == CONF1_ADDR_PORT);
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#else
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allow = 0;
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#endif
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if (!allow) {
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AcpiOsFree(devinfo);
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return (0);
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}
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@ -1317,7 +1316,6 @@ acpi_set_resource(device_t dev, device_t child, int type, int rid,
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AcpiOsFree(devinfo);
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}
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}
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#endif
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#ifdef INTRNG
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/* map with default for now */
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@ -1874,15 +1872,18 @@ acpi_isa_pnp_probe(device_t bus, device_t child, struct isa_pnp_id *ids)
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return_VALUE (result);
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}
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#if defined(__i386__) || defined(__amd64__)
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/*
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* Look for a MCFG table. If it is present, use the settings for
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* domain (segment) 0 to setup PCI config space access via the memory
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* map.
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*
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* On non-x86 architectures (arm64 for now), this will be done from the
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* PCI host bridge driver.
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*/
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static void
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acpi_enable_pcie(void)
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{
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#if defined(__i386__) || defined(__amd64__)
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ACPI_TABLE_HEADER *hdr;
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ACPI_MCFG_ALLOCATION *alloc, *end;
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ACPI_STATUS status;
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@ -1901,31 +1902,8 @@ acpi_enable_pcie(void)
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}
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alloc++;
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}
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}
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#elif defined(__aarch64__)
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static void
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acpi_enable_pcie(device_t child, int segment)
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{
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ACPI_TABLE_HEADER *hdr;
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ACPI_MCFG_ALLOCATION *alloc, *end;
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ACPI_STATUS status;
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status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
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if (ACPI_FAILURE(status))
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return;
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end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
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alloc = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
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while (alloc < end) {
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if (alloc->PciSegment == segment) {
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bus_set_resource(child, SYS_RES_MEMORY, 0,
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alloc->Address, 0x10000000);
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return;
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}
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alloc++;
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}
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}
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#endif
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}
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/*
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* Scan all of the ACPI namespace and attach child devices.
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@ -2016,9 +1994,6 @@ acpi_probe_child(ACPI_HANDLE handle, UINT32 level, void *context, void **status)
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{
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ACPI_DEVICE_INFO *devinfo;
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struct acpi_device *ad;
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#ifdef __aarch64__
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int segment;
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#endif
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struct acpi_prw_data prw;
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ACPI_OBJECT_TYPE type;
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ACPI_HANDLE h;
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@ -2121,13 +2096,6 @@ acpi_probe_child(ACPI_HANDLE handle, UINT32 level, void *context, void **status)
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ad->ad_cls_class = strtoul(devinfo->ClassCode.String,
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NULL, 16);
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}
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#ifdef __aarch64__
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if ((devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0) {
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if (ACPI_SUCCESS(acpi_GetInteger(handle, "_SEG", &segment))) {
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acpi_enable_pcie(child, segment);
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}
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}
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#endif
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AcpiOsFree(devinfo);
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}
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break;
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@ -63,8 +63,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/intr.h>
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#include "pcib_if.h"
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int pci_host_generic_acpi_attach(device_t);
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#include "acpi_bus_if.h"
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/* Assembling ECAM Configuration Address */
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#define PCIE_BUS_SHIFT 20
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@ -100,6 +99,9 @@ static int generic_pcie_acpi_probe(device_t dev);
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static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *);
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static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);
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/*
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* generic_pcie_acpi_probe - look for root bridge flag
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*/
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static int
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generic_pcie_acpi_probe(device_t dev)
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{
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@ -119,81 +121,201 @@ generic_pcie_acpi_probe(device_t dev)
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return (BUS_PROBE_GENERIC);
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}
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int
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/*
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* pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
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* 'produced' by this bridge
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*/
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static ACPI_STATUS
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pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
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{
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device_t dev = (device_t)arg;
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struct generic_pcie_acpi_softc *sc;
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struct rman *rm;
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rman_res_t min, max, off;
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int r;
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rm = NULL;
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sc = device_get_softc(dev);
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r = sc->base.nranges;
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switch (res->Type) {
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case ACPI_RESOURCE_TYPE_ADDRESS16:
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min = res->Data.Address16.Address.Minimum;
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max = res->Data.Address16.Address.Maximum;
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break;
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case ACPI_RESOURCE_TYPE_ADDRESS32:
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min = res->Data.Address32.Address.Minimum;
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max = res->Data.Address32.Address.Maximum;
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off = res->Data.Address32.Address.TranslationOffset;
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break;
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case ACPI_RESOURCE_TYPE_ADDRESS64:
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if (res->Data.Address.ResourceType != ACPI_MEMORY_RANGE)
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break;
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min = res->Data.Address64.Address.Minimum;
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max = res->Data.Address64.Address.Maximum;
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off = res->Data.Address64.Address.TranslationOffset;
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break;
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default:
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return (AE_OK);
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}
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/* Save detected ranges */
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if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE ||
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res->Data.Address.ResourceType == ACPI_IO_RANGE) {
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sc->base.ranges[r].pci_base = min;
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sc->base.ranges[r].phys_base = min + off;
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sc->base.ranges[r].size = max - min + 1;
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if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE)
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sc->base.ranges[r].flags |= FLAG_MEM;
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else if (res->Data.Address.ResourceType == ACPI_IO_RANGE)
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sc->base.ranges[r].flags |= FLAG_IO;
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sc->base.nranges++;
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} else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
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sc->base.bus_start = min;
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sc->base.bus_end = max;
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}
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return (AE_OK);
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}
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static int
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pci_host_acpi_get_ecam_resource(device_t dev)
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{
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struct generic_pcie_acpi_softc *sc;
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struct acpi_device *ad;
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struct resource_list *rl;
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ACPI_TABLE_HEADER *hdr;
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ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end;
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ACPI_HANDLE handle;
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ACPI_STATUS status;
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rman_res_t base, start, end;
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int found, val;
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sc = device_get_softc(dev);
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handle = acpi_get_handle(dev);
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/* Try MCFG first */
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status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
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if (ACPI_SUCCESS(status)) {
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found = FALSE;
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mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
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mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
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while (mcfg_entry < mcfg_end && !found) {
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if (mcfg_entry->PciSegment == sc->base.ecam &&
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mcfg_entry->StartBusNumber <= sc->base.bus_start &&
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mcfg_entry->EndBusNumber >= sc->base.bus_start)
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found = TRUE;
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else
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mcfg_entry++;
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}
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if (found) {
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if (mcfg_entry->EndBusNumber < sc->base.bus_end) {
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device_printf(dev, "bus end mismatch! expected %d found %d.\n",
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sc->base.bus_end, (int)mcfg_entry->EndBusNumber);
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sc->base.bus_end = mcfg_entry->EndBusNumber;
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}
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base = mcfg_entry->Address;
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} else {
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device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
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sc->base.bus_start, sc->base.bus_end);
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return (ENXIO);
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}
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} else {
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status = acpi_GetInteger(handle, "_CBA", &val);
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if (ACPI_SUCCESS(status))
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base = val;
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else
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return (ENXIO);
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}
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/* add as MEM rid 0 */
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ad = device_get_ivars(dev);
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rl = &ad->ad_rl;
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start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
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end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
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resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
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if (bootverbose)
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device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
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sc->base.bus_start, sc->base.bus_end, start, end);
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return (0);
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}
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static int
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pci_host_generic_acpi_attach(device_t dev)
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{
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struct generic_pcie_acpi_softc *sc;
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ACPI_HANDLE handle;
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uint64_t phys_base;
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uint64_t pci_base;
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uint64_t size;
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ACPI_STATUS status;
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int error, bus_start;
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int error;
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int tuple;
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sc = device_get_softc(dev);
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handle = acpi_get_handle(dev);
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/* Get Start bus number for the PCI host bus is from _BBN method */
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status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
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if (ACPI_FAILURE(status)) {
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device_printf(dev, "No _BBN, using start bus 0\n");
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sc->base.bus_start = 0;
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}
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sc->base.bus_end = 255;
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/* Get PCI Segment (domain) needed for MCFG lookup */
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status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
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if (ACPI_FAILURE(status)) {
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device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
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sc->base.ecam = 0;
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}
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/* Bus decode ranges */
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status = AcpiWalkResources(handle, "_CRS",
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pci_host_generic_acpi_parse_resource, (void *)dev);
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if (ACPI_FAILURE(status))
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return (ENXIO);
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/* Coherency attribute */
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if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
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sc->base.coherent = 0;
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if (bootverbose)
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device_printf(dev, "Bus is%s cache-coherent\n",
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sc->base.coherent ? "" : " not");
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if (!ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", &bus_start))) {
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sc->base.ecam = bus_start >> 7;
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sc->base.bus_start = bus_start & 0x7F;
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} else {
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sc->base.ecam = 0;
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sc->base.bus_start = 0;
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}
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sc->base.bus_end = 0xFF;
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/* add config space resource */
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pci_host_acpi_get_ecam_resource(dev);
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acpi_pcib_fetch_prt(dev, &sc->ap_prt);
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error = pci_host_generic_core_attach(dev);
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if (error != 0)
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return (error);
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status = AcpiWalkResources(handle, "_CRS",
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pci_host_generic_acpi_parse_resource, (void *)dev);
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if (ACPI_FAILURE(status))
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return (ENXIO);
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for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
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phys_base = sc->base.ranges[tuple].phys_base;
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pci_base = sc->base.ranges[tuple].pci_base;
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size = sc->base.ranges[tuple].size;
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if (phys_base == 0 || size == 0)
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continue; /* empty range element */
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if (sc->base.ranges[tuple].flags & FLAG_MEM) {
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error = rman_manage_region(&sc->base.mem_rman,
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phys_base, phys_base + size - 1);
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} else if (sc->base.ranges[tuple].flags & FLAG_IO) {
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error = rman_manage_region(&sc->base.io_rman,
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pci_base + PCI_IO_WINDOW_OFFSET,
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pci_base + PCI_IO_WINDOW_OFFSET + size - 1);
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} else
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continue;
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if (error) {
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device_printf(dev, "rman_manage_region() failed."
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"error = %d\n", error);
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rman_fini(&sc->base.mem_rman);
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return (error);
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}
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}
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static ACPI_STATUS
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pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg)
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{
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device_t dev = (device_t)arg;
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struct generic_pcie_acpi_softc *sc;
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rman_res_t min, max;
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int error;
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switch (res->Type) {
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case ACPI_RESOURCE_TYPE_ADDRESS32:
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min = (rman_res_t)res->Data.Address32.Address.Minimum;
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max = (rman_res_t)res->Data.Address32.Address.Maximum;
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break;
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case ACPI_RESOURCE_TYPE_ADDRESS64:
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min = (rman_res_t)res->Data.Address64.Address.Minimum;
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max = (rman_res_t)res->Data.Address64.Address.Maximum;
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break;
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default:
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return (AE_OK);
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}
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sc = device_get_softc(dev);
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error = rman_manage_region(&sc->base.mem_rman, min, max);
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if (error) {
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device_printf(dev, "unable to allocate %lx-%lx range\n", min, max);
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return (AE_NOT_FOUND);
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}
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device_printf(dev, "allocating %lx-%lx range\n", min, max);
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return (AE_OK);
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}
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static int
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generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result)
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@ -203,7 +325,7 @@ generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
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sc = device_get_softc(dev);
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if (index == PCIB_IVAR_BUS) {
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*result = sc->base.ecam * 0x80 + sc->base.bus_start;
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*result = sc->base.bus_start;
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return (0);
|
||||
}
|
||||
|
||||
@ -223,50 +345,62 @@ generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
|
||||
struct generic_pcie_acpi_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
|
||||
return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
|
||||
}
|
||||
|
||||
static struct resource *
|
||||
pci_host_generic_acpi_alloc_resource(device_t dev, device_t child, int type,
|
||||
int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
|
||||
{
|
||||
struct resource *res = NULL;
|
||||
|
||||
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
|
||||
struct generic_pcie_acpi_softc *sc;
|
||||
|
||||
if (type == PCI_RES_BUS) {
|
||||
sc = device_get_softc(dev);
|
||||
return (pci_domain_alloc_bus(sc->base.ecam, child, rid, start,
|
||||
end, count, flags));
|
||||
}
|
||||
#endif
|
||||
|
||||
if (type == SYS_RES_MEMORY)
|
||||
res = pci_host_generic_core_alloc_resource(dev, child, type,
|
||||
rid, start, end, count, flags);
|
||||
|
||||
if (res == NULL)
|
||||
res = bus_generic_alloc_resource(dev, child, type, rid, start, end,
|
||||
count, flags);
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*
|
||||
* Follow logic of FDT activate
|
||||
*/
|
||||
static int
|
||||
generic_pcie_acpi_activate_resource(device_t dev, device_t child, int type,
|
||||
int rid, struct resource *r)
|
||||
{
|
||||
struct generic_pcie_acpi_softc *sc;
|
||||
uint64_t phys_base;
|
||||
uint64_t pci_base;
|
||||
uint64_t size;
|
||||
int found;
|
||||
int res;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if ((res = rman_activate_resource(r)) != 0)
|
||||
return (res);
|
||||
|
||||
res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid,r);
|
||||
switch (type) {
|
||||
case SYS_RES_IOPORT:
|
||||
found = 0;
|
||||
for (i = 0; i < MAX_RANGES_TUPLES; i++) {
|
||||
pci_base = sc->base.ranges[i].pci_base;
|
||||
phys_base = sc->base.ranges[i].phys_base;
|
||||
size = sc->base.ranges[i].size;
|
||||
|
||||
if ((rid > pci_base) && (rid < (pci_base + size))) {
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found) {
|
||||
rman_set_start(r, rman_get_start(r) + phys_base);
|
||||
rman_set_end(r, rman_get_end(r) + phys_base);
|
||||
res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev),
|
||||
child, type, rid, r);
|
||||
} else {
|
||||
device_printf(dev,
|
||||
"Failed to activate IOPORT resource\n");
|
||||
res = 0;
|
||||
}
|
||||
break;
|
||||
case SYS_RES_MEMORY:
|
||||
case SYS_RES_IRQ:
|
||||
res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
|
||||
type, rid, r);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
@ -279,8 +413,17 @@ generic_pcie_acpi_deactivate_resource(device_t dev, device_t child, int type,
|
||||
if ((res = rman_deactivate_resource(r)) != 0)
|
||||
return (res);
|
||||
|
||||
res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, type,
|
||||
rid, r);
|
||||
switch (type) {
|
||||
case SYS_RES_IOPORT:
|
||||
case SYS_RES_MEMORY:
|
||||
case SYS_RES_IRQ:
|
||||
res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
|
||||
type, rid, r);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
@ -347,30 +490,25 @@ static int
|
||||
generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
|
||||
uintptr_t *id)
|
||||
{
|
||||
struct generic_pcie_acpi_softc *sc;
|
||||
int err;
|
||||
|
||||
/* Use the PCI RID to find the MSI ID */
|
||||
if (type == PCI_ID_MSI) {
|
||||
sc = device_get_softc(pci);
|
||||
type = PCI_ID_RID;
|
||||
err = pcib_get_id(pci, child, type, id);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
*id |= sc->base.ecam << 16;
|
||||
return (0);
|
||||
}
|
||||
|
||||
return (pcib_get_id(pci, child, type, id));
|
||||
/*
|
||||
* Use the PCI RID to find the MSI ID for now, we support only 1:1
|
||||
* mapping
|
||||
*
|
||||
* On aarch64, more complex mapping would come from IORT table
|
||||
*/
|
||||
if (type == PCI_ID_MSI)
|
||||
return (pcib_get_id(pci, child, PCI_ID_RID, id));
|
||||
else
|
||||
return (pcib_get_id(pci, child, type, id));
|
||||
}
|
||||
|
||||
static device_method_t generic_pcie_acpi_methods[] = {
|
||||
DEVMETHOD(device_probe, generic_pcie_acpi_probe),
|
||||
DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
|
||||
DEVMETHOD(bus_alloc_resource, pci_host_generic_acpi_alloc_resource),
|
||||
DEVMETHOD(bus_activate_resource, generic_pcie_acpi_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, generic_pcie_acpi_deactivate_resource),
|
||||
DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
|
||||
DEVMETHOD(bus_activate_resource, generic_pcie_acpi_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource,generic_pcie_acpi_deactivate_resource),
|
||||
|
||||
/* pcib interface */
|
||||
DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user