New features:
- Moved BCM5706S/5708S SerDes support to brgphy (since they are not technically TBI interfaces) - Added 2.5G support for BCM5708S Comments: Since this driver is shared with bge I tested several available controllers supported by bge and all worked as expected, however the list was not exhaustive. Need wider testing. MFC after: 4 weeks
This commit is contained in:
davidch
parent
17322fae92
commit
191cff0657
@ -68,8 +68,13 @@ static int brgphy_attach(device_t);
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struct brgphy_softc {
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struct mii_softc mii_sc;
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int mii_oui;
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int mii_model;
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int mii_rev;
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int serdes_flags; /* Keeps track of the serdes type used */
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#define BRGPHY_5706S 0x0001
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#define BRGPHY_5708S 0x0002
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int bce_phy_flags; /* PHY flags transferred from the MAC driver */
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};
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static device_method_t brgphy_methods[] = {
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@ -94,10 +99,9 @@ DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
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static int brgphy_service(struct mii_softc *, struct mii_data *, int);
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static void brgphy_setmedia(struct mii_softc *, int, int);
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static void brgphy_status(struct mii_softc *);
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static int brgphy_mii_phy_auto(struct mii_softc *);
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static void brgphy_mii_phy_auto(struct mii_softc *);
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static void brgphy_reset(struct mii_softc *);
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static void brgphy_loop(struct mii_softc *);
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static int bcm5706_is_tbi(device_t);
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static void brgphy_enable_loopback(struct mii_softc *);
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static void bcm5401_load_dspcode(struct mii_softc *);
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static void bcm5411_load_dspcode(struct mii_softc *);
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static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
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@ -117,7 +121,7 @@ static const struct mii_phydesc brgphys[] = {
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MII_PHY_DESC(xxBROADCOM, BCM5703),
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MII_PHY_DESC(xxBROADCOM, BCM5704),
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MII_PHY_DESC(xxBROADCOM, BCM5705),
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MII_PHY_DESC(xxBROADCOM, BCM5706C),
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MII_PHY_DESC(xxBROADCOM, BCM5706),
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MII_PHY_DESC(xxBROADCOM, BCM5714),
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MII_PHY_DESC(xxBROADCOM, BCM5750),
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MII_PHY_DESC(xxBROADCOM, BCM5752),
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@ -126,79 +130,157 @@ static const struct mii_phydesc brgphys[] = {
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MII_PHY_DESC(xxBROADCOM, BCM5708C),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
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MII_PHY_END
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};
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/* Search for our PHY in the list of known PHYs */
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static int
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brgphy_probe(device_t dev)
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{
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struct mii_attach_args *ma;
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int error;
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error = mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT);
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if (error != BUS_PROBE_DEFAULT)
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return (error);
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ma = device_get_ivars(dev);
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if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
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MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5706C) {
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/*
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* Broadcom uses the same MII model ID on two
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* different types of phys. The first is found on the
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* BCM 5706 and is supported by this driver. The
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* other is found on the BCM 5706S and 5708S and is
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* supported by the gentbi(4) driver, so we check to
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* see if this phy is supported by gentbi(4) and fail
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* the probe if so.
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*/
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if (bcm5706_is_tbi(dev))
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return (ENXIO);
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}
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return (error);
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return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
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}
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/* Attach the PHY to the MII bus */
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static int
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brgphy_attach(device_t dev)
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{
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struct brgphy_softc *bsc;
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struct bge_softc *bge_sc = NULL;
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struct bce_softc *bce_sc = NULL;
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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struct ifnet *ifp;
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int fast_ether;
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bsc = device_get_softc(dev);
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sc = &bsc->mii_sc;
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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/*
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* At least some variants wedge when isolating, so never allow
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* non-zero instances! At least some also don't support loopback.
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*/
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if (mii->mii_instance != 0)
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panic("%s: ignoring this PHY, non-zero instance", __func__);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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/* Initialize mii_softc structure */
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = brgphy_service;
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sc->mii_pdata = mii;
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sc->mii_anegticks = MII_ANEGTICKS_GIGE;
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sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
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mii->mii_instance++;
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/* Initialize brgphy_softc structure */
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bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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bsc->mii_model = MII_MODEL(ma->mii_id2);
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bsc->mii_rev = MII_REV(ma->mii_id2);
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bsc->serdes_flags = 0;
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fast_ether = 0;
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if (bootverbose)
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device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
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bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
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/* Handle any special cases based on the PHY ID */
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switch (bsc->mii_oui) {
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case MII_OUI_BROADCOM:
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break;
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case MII_OUI_xxBROADCOM:
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switch (bsc->mii_model) {
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case MII_MODEL_xxBROADCOM_BCM5706:
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/*
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* The 5464 PHY used in the 5706 supports both copper
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* and fiber interfaces over GMII. Need to check the
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* shadow registers to see which mode is actually
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* in effect, and therefore whether we have 5706C or
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* 5706S.
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*/
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PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
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BRGPHY_SHADOW_1C_MODE_CTRL);
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if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
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BRGPHY_SHADOW_1C_ENA_1000X) {
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bsc->serdes_flags |= BRGPHY_5706S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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}
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break;
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} break;
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case MII_OUI_xxBROADCOM_ALT1:
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switch (bsc->mii_model) {
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case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
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bsc->serdes_flags |= BRGPHY_5708S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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} break;
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default:
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device_printf(dev, "Unrecognized OUI for PHY!\n");
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}
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ifp = sc->mii_pdata->mii_ifp;
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/* Find the MAC driver associated with this PHY. */
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if (strcmp(ifp->if_dname, "bge") == 0) {
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bge_sc = ifp->if_softc;
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} else if (strcmp(ifp->if_dname, "bce") == 0) {
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bce_sc = ifp->if_softc;
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}
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/* Todo: Need to add additional controllers such as 5906 & 5787F */
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/* The 590x chips are 10/100 only. */
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if (bge_sc &&
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pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
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(pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
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pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) {
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fast_ether = 1;
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sc->mii_anegticks = MII_ANEGTICKS;
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}
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brgphy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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/* Create an instance of Ethernet media. */
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO);
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/* Add the supported media types */
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
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BRGPHY_S10);
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printf("10baseT, ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
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BRGPHY_S10 | BRGPHY_BMCR_FDX);
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printf("10baseT-FDX, ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
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BRGPHY_S100);
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printf("100baseTX, ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
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BRGPHY_S100 | BRGPHY_BMCR_FDX);
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printf("100baseTX-FDX, ");
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if (fast_ether == 0) {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
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BRGPHY_S1000);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
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BRGPHY_S1000 | BRGPHY_BMCR_FDX);
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printf("1000baseTX-FDX, ");
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}
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} else {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
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BRGPHY_S1000 | BRGPHY_BMCR_FDX);
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printf("1000baseSX-FDX, ");
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/* 2.5G support is a software enabled feature on the 5708S */
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if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
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printf("2500baseSX-FDX, ");
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}
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}
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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printf("auto\n");
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#undef ADD
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return (0);
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}
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@ -208,29 +290,39 @@ brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int error = 0;
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int val;
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switch (cmd) {
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case MII_POLLSTAT:
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/* If we're not polling our PHY instance, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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goto brgphy_service_exit;
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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PHY_WRITE(sc, MII_BMCR,
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PHY_READ(sc, MII_BMCR) | BMCR_ISO);
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goto brgphy_service_exit;
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}
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/* If the interface is not up, don't do anything. */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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/* Todo: Why is this here? Is it really needed? */
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brgphy_reset(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/* If we're already in auto mode, just return. */
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if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void)brgphy_mii_phy_auto(sc);
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brgphy_mii_phy_auto(sc);
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break;
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case IFM_2500_SX:
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case IFM_1000_SX:
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case IFM_1000_T:
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case IFM_100_TX:
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case IFM_10_T:
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@ -238,21 +330,23 @@ brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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mii->mii_ifp->if_flags & IFF_LINK0);
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break;
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default:
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return (EINVAL);
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error = EINVAL;
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goto brgphy_service_exit;
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}
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break;
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case MII_TICK:
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/* If we're not currently selected, just return. */
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/* Bail if we're not currently selected. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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goto brgphy_service_exit;
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/* Is the interface even up? */
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/* Bail if the interface isn't up. */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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goto brgphy_service_exit;
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/* Only used for autonegotiation. */
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/* Bail if autoneg isn't in process. */
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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sc->mii_ticks = 0; /* Reset autoneg timer. */
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sc->mii_ticks = 0;
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break;
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}
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@ -260,21 +354,27 @@ brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process.
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*/
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if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) {
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val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (val & BMSR_LINK) {
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sc->mii_ticks = 0; /* Reset autoneg timer. */
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break;
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}
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#if 0
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/* Todo: Is this correct? */
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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#endif
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/* Only retry autonegotiation every mii_anegticks seconds. */
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if (sc->mii_ticks <= sc->mii_anegticks)
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return (0);
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goto brgphy_service_exit;
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/* Retry autonegotiation */
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sc->mii_ticks = 0;
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(void)brgphy_mii_phy_auto(sc);
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brgphy_mii_phy_auto(sc);
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break;
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}
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@ -288,30 +388,42 @@ brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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switch (bsc->mii_model) {
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case MII_MODEL_xxBROADCOM_BCM5400:
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bcm5401_load_dspcode(sc);
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switch (bsc->mii_oui) {
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case MII_OUI_BROADCOM:
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break;
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case MII_MODEL_xxBROADCOM_BCM5401:
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if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
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case MII_OUI_xxBROADCOM:
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switch (bsc->mii_model) {
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case MII_MODEL_xxBROADCOM_BCM5400:
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bcm5401_load_dspcode(sc);
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break;
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case MII_MODEL_xxBROADCOM_BCM5401:
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if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
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bcm5401_load_dspcode(sc);
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break;
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case MII_MODEL_xxBROADCOM_BCM5411:
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bcm5411_load_dspcode(sc);
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break;
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}
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break;
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case MII_MODEL_xxBROADCOM_BCM5411:
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bcm5411_load_dspcode(sc);
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case MII_OUI_xxBROADCOM_ALT1:
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break;
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}
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}
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mii_phy_update(sc, cmd);
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return (0);
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brgphy_service_exit:
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return (error);
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}
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static void
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brgphy_setmedia(struct mii_softc *sc, int media, int master)
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{
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struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
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int bmcr, gig;
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int bmcr = 0, gig;
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switch (IFM_SUBTYPE(media)) {
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case IFM_2500_SX:
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break;
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case IFM_1000_SX:
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case IFM_1000_T:
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bmcr = BRGPHY_S1000;
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break;
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@ -330,20 +442,20 @@ brgphy_setmedia(struct mii_softc *sc, int media, int master)
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gig = BRGPHY_1000CTL_AHD;
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}
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brgphy_loop(sc);
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brgphy_enable_loopback(sc);
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PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
|
||||
PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
|
||||
|
||||
if (IFM_SUBTYPE(media) != IFM_1000_T)
|
||||
return;
|
||||
if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
|
||||
goto brgphy_setmedia_exit;
|
||||
|
||||
PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
|
||||
PHY_WRITE(sc, BRGPHY_MII_BMCR,
|
||||
bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
|
||||
|
||||
if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
|
||||
return;
|
||||
goto brgphy_setmedia_exit;
|
||||
|
||||
/*
|
||||
* When setting the link manually, one side must be the master and
|
||||
@ -359,133 +471,181 @@ brgphy_setmedia(struct mii_softc *sc, int media, int master)
|
||||
PHY_WRITE(sc, BRGPHY_MII_1000CTL,
|
||||
gig | BRGPHY_1000CTL_MSE);
|
||||
}
|
||||
brgphy_setmedia_exit:
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set the media status based on the PHY settings. */
|
||||
/* IFM_FLAG0 = 0 (RX flow control disabled | 1 (enabled) */
|
||||
/* IFM_FLAG1 = 0 (TX flow control disabled | 1 (enabled) */
|
||||
static void
|
||||
brgphy_status(struct mii_softc *sc)
|
||||
{
|
||||
struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
int aux, bmcr, bmsr;
|
||||
int aux, bmcr, bmsr, anar, anlpar, xstat, val;
|
||||
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
|
||||
bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
|
||||
bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
|
||||
bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
|
||||
bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
|
||||
anar = PHY_READ(sc, BRGPHY_MII_ANAR);
|
||||
anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
|
||||
|
||||
if (aux & BRGPHY_AUXSTS_LINK)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
/* Loopback is enabled. */
|
||||
if (bmcr & BRGPHY_BMCR_LOOP) {
|
||||
|
||||
if (bmcr & BRGPHY_BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
}
|
||||
|
||||
/* Autoneg is still in progress. */
|
||||
if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
|
||||
(bmsr & BRGPHY_BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
goto brgphy_status_exit;
|
||||
}
|
||||
|
||||
if (aux & BRGPHY_AUXSTS_LINK) {
|
||||
switch (aux & BRGPHY_AUXSTS_AN_RES) {
|
||||
case BRGPHY_RES_1000FD:
|
||||
mii->mii_media_active |= IFM_1000_T | IFM_FDX;
|
||||
break;
|
||||
case BRGPHY_RES_1000HD:
|
||||
mii->mii_media_active |= IFM_1000_T | IFM_HDX;
|
||||
break;
|
||||
case BRGPHY_RES_100FD:
|
||||
mii->mii_media_active |= IFM_100_TX | IFM_FDX;
|
||||
break;
|
||||
case BRGPHY_RES_100T4:
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
break;
|
||||
case BRGPHY_RES_100HD:
|
||||
mii->mii_media_active |= IFM_100_TX | IFM_HDX;
|
||||
break;
|
||||
case BRGPHY_RES_10FD:
|
||||
mii->mii_media_active |= IFM_10_T | IFM_FDX;
|
||||
break;
|
||||
case BRGPHY_RES_10HD:
|
||||
mii->mii_media_active |= IFM_10_T | IFM_HDX;
|
||||
break;
|
||||
default:
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
break;
|
||||
/* Autoneg is enabled and complete, link should be up. */
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
|
||||
|
||||
/* If copper link is up, get the negotiated speed/duplex. */
|
||||
if (aux & BRGPHY_AUXSTS_LINK) {
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
switch (aux & BRGPHY_AUXSTS_AN_RES) {
|
||||
case BRGPHY_RES_1000FD:
|
||||
mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
|
||||
case BRGPHY_RES_1000HD:
|
||||
mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
|
||||
case BRGPHY_RES_100FD:
|
||||
mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
|
||||
case BRGPHY_RES_100T4:
|
||||
mii->mii_media_active |= IFM_100_T4; break;
|
||||
case BRGPHY_RES_100HD:
|
||||
mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
|
||||
case BRGPHY_RES_10FD:
|
||||
mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
|
||||
case BRGPHY_RES_10HD:
|
||||
mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
|
||||
default:
|
||||
mii->mii_media_active |= IFM_NONE; break;
|
||||
}
|
||||
}
|
||||
} else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
} else {
|
||||
/* If serdes link is up, get the negotiated speed/duplex. */
|
||||
if (bmsr & BRGPHY_BMSR_LINK) {
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
}
|
||||
|
||||
/* Check the link speed/duplex based on the PHY type. */
|
||||
if (bsc->serdes_flags & BRGPHY_5706S) {
|
||||
mii->mii_media_active |= IFM_1000_SX;
|
||||
|
||||
/* If autoneg enabled, read negotiated duplex settings */
|
||||
if (bmcr & BRGPHY_BMCR_AUTOEN) {
|
||||
val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
|
||||
if (val & BRGPHY_SERDES_ANAR_FDX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
}
|
||||
|
||||
} else if (bsc->serdes_flags & BRGPHY_5708S) {
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
|
||||
xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
|
||||
|
||||
/* Todo: Create #defines for hard coded values */
|
||||
switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
|
||||
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
|
||||
mii->mii_media_active |= IFM_10_FL; break;
|
||||
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
|
||||
mii->mii_media_active |= IFM_100_FX; break;
|
||||
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
|
||||
mii->mii_media_active |= IFM_1000_SX; break;
|
||||
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
|
||||
mii->mii_media_active |= IFM_2500_SX; break;
|
||||
}
|
||||
|
||||
if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Todo: Change bge/bce to use these settings. */
|
||||
|
||||
/* Fetch flow control settings from the PHY */
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
/* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */
|
||||
if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
|
||||
mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
|
||||
} else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
|
||||
(anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
|
||||
mii->mii_media_active |= IFM_FLAG1;
|
||||
} else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
|
||||
!(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
|
||||
mii->mii_media_active |= IFM_FLAG0;
|
||||
}
|
||||
}
|
||||
/* Todo: Add support for fiber settings too. */
|
||||
#endif
|
||||
|
||||
|
||||
brgphy_status_exit:
|
||||
return;
|
||||
}
|
||||
|
||||
static int
|
||||
static void
|
||||
brgphy_mii_phy_auto(struct mii_softc *sc)
|
||||
{
|
||||
struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
|
||||
int ktcr = 0;
|
||||
|
||||
brgphy_loop(sc);
|
||||
brgphy_reset(sc);
|
||||
|
||||
/* Enable flow control in the advertisement register. */
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
/* Pause capability advertisement (pause capable & asymmetric) */
|
||||
PHY_WRITE(sc, BRGPHY_MII_ANAR,
|
||||
BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
|
||||
BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
|
||||
} else {
|
||||
PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
|
||||
BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
|
||||
}
|
||||
|
||||
/* Enable speed in the 1000baseT control register */
|
||||
ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
|
||||
if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
|
||||
ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
|
||||
PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
|
||||
ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
|
||||
DELAY(1000);
|
||||
PHY_WRITE(sc, BRGPHY_MII_ANAR,
|
||||
BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
|
||||
DELAY(1000);
|
||||
PHY_WRITE(sc, BRGPHY_MII_BMCR,
|
||||
BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
|
||||
|
||||
/* Start autonegotiation */
|
||||
PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
|
||||
PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
|
||||
return (EJUSTRETURN);
|
||||
|
||||
}
|
||||
|
||||
/* Enable loopback to force the link down. */
|
||||
static void
|
||||
brgphy_loop(struct mii_softc *sc)
|
||||
brgphy_enable_loopback(struct mii_softc *sc)
|
||||
{
|
||||
int i;
|
||||
|
||||
PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
|
||||
for (i = 0; i < 15000; i++) {
|
||||
if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) {
|
||||
#if 0
|
||||
device_printf(sc->mii_dev, "looped %d\n", i);
|
||||
#endif
|
||||
if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
|
||||
break;
|
||||
}
|
||||
DELAY(10);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Check to see if a 5706 phy is really a SerDes phy. Copied from
|
||||
* gentbi_probe().
|
||||
*/
|
||||
static int
|
||||
bcm5706_is_tbi(device_t dev)
|
||||
{
|
||||
device_t parent;
|
||||
struct mii_attach_args *ma;
|
||||
int bmsr, extsr;
|
||||
|
||||
parent = device_get_parent(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
|
||||
bmsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_BMSR);
|
||||
if ((bmsr & BMSR_EXTSTAT) == 0 || (bmsr & BMSR_MEDIAMASK) != 0)
|
||||
return (0);
|
||||
|
||||
extsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_EXTSR);
|
||||
if (extsr & (EXTSR_1000TFDX|EXTSR_1000THDX))
|
||||
return (0);
|
||||
|
||||
if (extsr & (EXTSR_1000XFDX|EXTSR_1000XHDX))
|
||||
return (1);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Turn off tap power management on 5401. */
|
||||
static void
|
||||
bcm5401_load_dspcode(struct mii_softc *sc)
|
||||
@ -577,7 +737,7 @@ brgphy_fixup_adjust_trim(struct mii_softc *sc)
|
||||
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
||||
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
|
||||
{ BRGPHY_MII_DSP_RW_PORT, 0x110b },
|
||||
{ BRGPHY_MII_TEST1, 0x0014 },
|
||||
{ BRGPHY_MII_TEST1, 0x0014 },
|
||||
{ BRGPHY_MII_AUXCTL, 0x0400 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
@ -687,8 +847,8 @@ brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
|
||||
val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
|
||||
|
||||
val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
|
||||
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
||||
val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
|
||||
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
||||
val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
|
||||
}
|
||||
}
|
||||
|
||||
@ -702,16 +862,25 @@ brgphy_reset(struct mii_softc *sc)
|
||||
|
||||
mii_phy_reset(sc);
|
||||
|
||||
switch (bsc->mii_model) {
|
||||
case MII_MODEL_xxBROADCOM_BCM5400:
|
||||
bcm5401_load_dspcode(sc);
|
||||
/* Handle any PHY specific procedures to finish the reset. */
|
||||
switch (bsc->mii_oui) {
|
||||
case MII_OUI_BROADCOM:
|
||||
break;
|
||||
case MII_MODEL_xxBROADCOM_BCM5401:
|
||||
if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
|
||||
case MII_OUI_xxBROADCOM:
|
||||
switch (bsc->mii_model) {
|
||||
case MII_MODEL_xxBROADCOM_BCM5400:
|
||||
bcm5401_load_dspcode(sc);
|
||||
break;
|
||||
case MII_MODEL_xxBROADCOM_BCM5401:
|
||||
if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
|
||||
bcm5401_load_dspcode(sc);
|
||||
break;
|
||||
case MII_MODEL_xxBROADCOM_BCM5411:
|
||||
bcm5411_load_dspcode(sc);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MII_MODEL_xxBROADCOM_BCM5411:
|
||||
bcm5411_load_dspcode(sc);
|
||||
case MII_OUI_xxBROADCOM_ALT1:
|
||||
break;
|
||||
}
|
||||
|
||||
@ -724,7 +893,7 @@ brgphy_reset(struct mii_softc *sc)
|
||||
bce_sc = ifp->if_softc;
|
||||
}
|
||||
|
||||
/* Handle any NetXtreme/bge workarounds. */
|
||||
/* Handle any bge (NetXtreme/NetLink) workarounds. */
|
||||
if (bge_sc) {
|
||||
/* Fix up various bugs */
|
||||
if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
|
||||
@ -757,9 +926,64 @@ brgphy_reset(struct mii_softc *sc)
|
||||
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
|
||||
~BRGPHY_PHY_EXTCTL_3_LED);
|
||||
}
|
||||
/* Handle any bce (NetXtreme II) workarounds. */
|
||||
} else if (bce_sc) {
|
||||
brgphy_fixup_ber_bug(sc);
|
||||
brgphy_jumbo_settings(sc, ifp->if_mtu);
|
||||
brgphy_ethernet_wirespeed(sc);
|
||||
|
||||
if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
|
||||
BCE_CHIP_BOND_ID(bce_sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
|
||||
|
||||
/* Store autoneg capabilities/results in digital block (Page 0) */
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
|
||||
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
|
||||
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
|
||||
|
||||
/* Enable fiber mode and autodetection */
|
||||
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
|
||||
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
|
||||
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
|
||||
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
|
||||
|
||||
/* Enable parallel detection */
|
||||
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
|
||||
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
|
||||
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
|
||||
|
||||
/* Advertise 2.5G support through next page during autoneg */
|
||||
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
|
||||
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
|
||||
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
|
||||
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
|
||||
|
||||
/* Increase TX signal amplitude */
|
||||
if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
|
||||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
|
||||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
||||
BRGPHY_5708S_TX_MISC_PG5);
|
||||
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
|
||||
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
||||
BRGPHY_5708S_DIG_PG0);
|
||||
}
|
||||
|
||||
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
|
||||
if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
|
||||
(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
||||
BRGPHY_5708S_TX_MISC_PG5);
|
||||
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
|
||||
bce_sc->bce_port_hw_cfg &
|
||||
BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
|
||||
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
||||
BRGPHY_5708S_DIG_PG0);
|
||||
}
|
||||
} else {
|
||||
brgphy_fixup_ber_bug(sc);
|
||||
brgphy_jumbo_settings(sc, ifp->if_mtu);
|
||||
brgphy_ethernet_wirespeed(sc);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -39,21 +39,21 @@
|
||||
* Broadcom BCM5400 registers
|
||||
*/
|
||||
|
||||
#define BRGPHY_MII_BMCR 0x00
|
||||
#define BRGPHY_BMCR_RESET 0x8000
|
||||
#define BRGPHY_BMCR_LOOP 0x4000
|
||||
#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
|
||||
#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
|
||||
#define BRGPHY_MII_BMCR 0x00
|
||||
#define BRGPHY_BMCR_RESET 0x8000
|
||||
#define BRGPHY_BMCR_LOOP 0x4000
|
||||
#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
|
||||
#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
|
||||
#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
|
||||
#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define BRGPHY_S10 0 /* 10mbps */
|
||||
#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define BRGPHY_S10 0 /* 10mbps */
|
||||
|
||||
#define BRGPHY_MII_BMSR 0x01
|
||||
#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
|
||||
@ -209,7 +209,7 @@
|
||||
#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */
|
||||
#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */
|
||||
#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */
|
||||
#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HDC */
|
||||
#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */
|
||||
#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
|
||||
#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */
|
||||
#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */
|
||||
@ -261,10 +261,103 @@
|
||||
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
|
||||
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: Shared SerDes PHY register definitions */
|
||||
/*******************************************************/
|
||||
|
||||
/* SerDes autoneg is different from copper */
|
||||
#define BRGPHY_SERDES_ANAR 0x04
|
||||
#define BRGPHY_SERDES_ANAR_FDX 0x0020
|
||||
#define BRGPHY_SERDES_ANAR_HDX 0x0040
|
||||
#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
|
||||
#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
|
||||
|
||||
#define BRGPHY_SERDES_ANLPAR 0x05
|
||||
#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
|
||||
#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
|
||||
#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
|
||||
#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
|
||||
|
||||
/*******************************************************/
|
||||
/* End: Shared SerDes PHY register definitions */
|
||||
/*******************************************************/
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: PHY register values for the 5706 PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/*
|
||||
* Shadow register 0x1C, bit 15 is write enable,
|
||||
* bits 14-10 select function (0x00 to 0x1F).
|
||||
*/
|
||||
#define BRGPHY_MII_SHADOW_1C 0x1C
|
||||
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
|
||||
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
|
||||
|
||||
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
|
||||
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
|
||||
/* When set, Regs 0-0x0F are 1000X, else 1000T */
|
||||
#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
|
||||
|
||||
#define BRGPHY_MII_TEST1 0x1E
|
||||
#define BRGPHY_TEST1_TRIM_EN 0x0010
|
||||
#define BRGPHY_TEST1_CRC_EN 0x8000
|
||||
|
||||
#define BRGPHY_MII_TEST2 0x1F
|
||||
|
||||
/*******************************************************/
|
||||
/* End: PHY register values for the 5706 PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/*******************************************************/
|
||||
/* Begin: PHY register values for the 5708S SerDes PHY */
|
||||
/*******************************************************/
|
||||
|
||||
/* Autoneg Next Page Transmit 1 Regiser */
|
||||
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
|
||||
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
|
||||
|
||||
/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
|
||||
#define BRGPHY_5708S_BLOCK_ADDR 0x1f
|
||||
#define BRGPHY_5708S_DIG_PG0 0x0000
|
||||
#define BRGPHY_5708S_DIG3_PG2 0x0002
|
||||
#define BRGPHY_5708S_TX_MISC_PG5 0x0005
|
||||
|
||||
/* 5708S SerDes "Digital" Registers (page 0) */
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
|
||||
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
|
||||
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
|
||||
|
||||
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
|
||||
#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
|
||||
|
||||
/* 5708S SerDes "Digital 3" Registers (page 2) */
|
||||
#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
|
||||
#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
|
||||
|
||||
/* 5708S SerDes "TX Misc" Registers (page 5) */
|
||||
#define BRGPHY_5708S_PG5_2500STATUS1 0x10
|
||||
#define BRGPHY_5708S_PG5_TXACTL1 0x15
|
||||
#define BRGPHY_5708S_PG5_TXACTL3 0x17
|
||||
|
||||
/*******************************************************/
|
||||
/* End: PHY register values for the 5708S SerDes PHY */
|
||||
/*******************************************************/
|
||||
|
||||
#define BRGPHY_INTRS \
|
||||
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
|
||||
|
||||
|
||||
@ -124,7 +124,7 @@ model xxBROADCOM BCM5411 0x0007 BCM5411 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5754 0x000e BCM5754 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5752 0x0010 BCM5752 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5701 0x0011 BCM5701 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5706C 0x0015 BCM5706C 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5706 0x0015 BCM5706 10/100/1000baseTX/SX PHY
|
||||
model xxBROADCOM BCM5703 0x0016 BCM5703 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5704 0x0019 BCM5704 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5705 0x001a BCM5705 10/100/1000baseTX PHY
|
||||
@ -134,6 +134,7 @@ model xxBROADCOM BCM5780 0x0035 BCM5780 10/100/1000baseTX PHY
|
||||
model xxBROADCOM BCM5708C 0x0036 BCM5708C 10/100/1000baseTX PHY
|
||||
model xxBROADCOM_ALT1 BCM5755 0x000c BCM5755 10/100/1000baseTX PHY
|
||||
model xxBROADCOM_ALT1 BCM5787 0x000e BCM5787 10/100/1000baseTX PHY
|
||||
model xxBROADCOM_ALT1 BCM5708S 0x0015 BCM5708S 1000/2500BaseSX PHY
|
||||
|
||||
/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
|
||||
model CICADA CS8201 0x0001 Cicada CS8201 10/100/1000TX PHY
|
||||
|
||||
Loading…
Reference in New Issue
Block a user