From 19235437178eac3f2b55f1839b6de731b49b1a4a Mon Sep 17 00:00:00 2001 From: adrian Date: Sat, 29 Jan 2011 12:30:13 +0000 Subject: [PATCH] Fix some errors introduced w/ the last commit; fix setting RTS/CTS in the 11n rate scenario. * I messed up a couple of things in if_athvar.h; so fix that. * Undo some guesswork done in ar5416Set11nRateScenario() and introduce a flags parameter which lets the caller set a few things. To begin with, this includes whether to do RTS or CTS protection. * If both RTS and CTS is set, only do RTS. Both RTS and CTS shouldn't be set on a frame. --- sys/dev/ath/ath_hal/ar5416/ar5416.h | 2 +- sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c | 46 ++++++++++++------------ sys/dev/ath/if_athvar.h | 10 ++---- 3 files changed, 28 insertions(+), 30 deletions(-) diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416.h b/sys/dev/ath/ath_hal/ar5416/ar5416.h index ef83ab6ac80f..8a9946e2bc5d 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416.h +++ b/sys/dev/ath/ath_hal/ar5416/ar5416.h @@ -236,7 +236,7 @@ extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu); extern u_int ar5416GetGlobalTxTimeout(struct ath_hal *ah); extern void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, u_int durUpdateEn, u_int rtsctsRate, HAL_11N_RATE_SERIES series[], - u_int nseries); + u_int nseries, u_int flags); extern void ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims); extern void ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds); extern void ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, u_int burstDuration); diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c b/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c index 3f3d00a5c084..af3d1d99e8a5 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c @@ -612,13 +612,36 @@ ar5416GetGlobalTxTimeout(struct ath_hal *ah) void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, u_int durUpdateEn, u_int rtsctsRate, - HAL_11N_RATE_SERIES series[], u_int nseries) + HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags) { struct ar5416_desc *ads = AR5416DESC(ds); + uint32_t ds_ctl0; HALASSERT(nseries == 4); (void)nseries; + /* + * Only one of RTS and CTS enable must be set. + * If a frame has both set, just do RTS protection - + * that's enough to satisfy legacy protection. + */ + if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + ds_ctl0 = ads->ds_ctl0; + + if (flags & HAL_TXDESC_RTSENA) { + ds_ctl0 &= ~AR_CTSEnable; + ds_ctl0 |= AR_RTSEnable; + } else { + ds_ctl0 &= ~AR_RTSEnable; + ds_ctl0 |= AR_CTSEnable; + } + + ads->ds_ctl0 = ds_ctl0; + } else { + ads->ds_ctl0 = + (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); + } + ads->ds_ctl2 = set11nTries(series, 0) | set11nTries(series, 1) @@ -642,27 +665,6 @@ ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, | set11nRateFlags(series, 2) | set11nRateFlags(series, 3) | SM(rtsctsRate, AR_RTSCTSRate); - - /* - * Enable RTSCTS if any of the series is flagged for RTSCTS, - * but only if CTS is not enabled. - */ - /* - * FIXME : the entire RTS/CTS handling should be moved to this - * function (by passing the global RTS/CTS flags to this function). - * currently it is split between this function and the - * setupFiirstDescriptor. with this current implementation there - * is an implicit assumption that setupFirstDescriptor is called - * before this function. - */ - if (((series[0].RateFlags & HAL_RATESERIES_RTS_CTS) || - (series[1].RateFlags & HAL_RATESERIES_RTS_CTS) || - (series[2].RateFlags & HAL_RATESERIES_RTS_CTS) || - (series[3].RateFlags & HAL_RATESERIES_RTS_CTS) ) && - (ads->ds_ctl0 & AR_CTSEnable) == 0) { - ads->ds_ctl0 |= AR_RTSEnable; - ads->ds_ctl0 &= ~AR_CTSEnable; - } } void diff --git a/sys/dev/ath/if_athvar.h b/sys/dev/ath/if_athvar.h index 6a2616a6b84b..4cec4cec1b9b 100644 --- a/sys/dev/ath/if_athvar.h +++ b/sys/dev/ath/if_athvar.h @@ -655,7 +655,7 @@ void ath_intr(void *); ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) #define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ - _ cipher, _delims, _seglen, _first, _last) \ + _cipher, _delims, _seglen, _first, _last) \ ((*(_ah)->ah_chainTxDesc((_ah), (_ds), (_pktlen), (_hdrlen), \ (_type), (_keyix), (_cipher), (_delims), (_seglen), \ (_first), (_last)))) @@ -665,18 +665,14 @@ void ath_intr(void *); (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) -#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns) \ +#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ - (_series), (_ns))) + (_series), (_ns), (_flags))) #define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ ((*(_ah)->ah_set11nAggrMiddle((_ah), (_ds), (_num)))) #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) - #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ - ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) - #define ath_hal_gpioset(_ah, _gpio, _b) \ - #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) #define ath_hal_gpioset(_ah, _gpio, _b) \