Enable power management for E500 cores. Use "doze" for now to make

sure the caches remain coherent. For single-core configurations and
with busdma changes we could eventually switch to "nap" and force
a D-cache invalidation as part of the DMA completion. To this end,
clear PSL_WE until after we handled the decrementer or external
interrupt as it tells us whether we just woke up or not.

sys/powerpc/booke/interrupt.c

@@ -123,6 +123,7 @@ powerpc_decr_interrupt(struct trapframe *framep)
 	decr_intr(framep);
 	atomic_subtract_int(&td->td_intr_nesting_level, 1);
 	critical_exit();
+	framep->srr1 &= ~PSL_WE;
 }
 
 /*
@@ -135,4 +136,5 @@ powerpc_extr_interrupt(struct trapframe *framep)
 	critical_enter();
 	PIC_DISPATCH(pic, framep);
 	critical_exit();
+	framep->srr1 &= ~PSL_WE;
 }

sys/powerpc/booke/machdep.c

@@ -706,6 +706,7 @@ cpu_idle (int busy)
 	register_t msr;
 
 	msr = mfmsr();
+
 #ifdef INVARIANTS
 	if ((msr & PSL_EE) != PSL_EE) {
 		struct thread *td = curthread;
@@ -713,19 +714,10 @@ cpu_idle (int busy)
 		panic("ints disabled in idleproc!");
 	}
 #endif
-#if 0
-	/*
-	 * Freescale E500 core RM section 6.4.1
-	 */
-	msr = msr | PSL_WE;
 
-	__asm__("	msync;"
-		"	mtmsr	%0;"
-		"	isync;"
-		"loop:	b	loop" :
-		/* no output */	:
-		"r" (msr));
-#endif
+	/* Freescale E500 core RM section 6.4.1. */
+	msr = msr | PSL_WE;
+	__asm __volatile("msync; mtmsr %0; isync" :: "r" (msr));
 }
 
 int

sys/powerpc/powerpc/cpu.c

@@ -433,6 +433,13 @@ cpu_e500_setup(int cpuid, uint16_t vers)
 	register_t hid0;
 
 	hid0 = mfspr(SPR_HID0);
+
+	/* Programe power-management mode. */
+	hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
+	hid0 |= HID0_DOZE;
+
+	mtspr(SPR_HID0, hid0);
+
 	printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
 }