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powerpc/pseries: EOI interrupts in XICS by setting lowest priority

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Discussing with Benjamin Herrenschmidt, OPAL_INT_GET_XIRR masks the
returned priority, so must be resumed before more interrupts can be
handled at this priority.  Since there are only two priorities used in
FreeBSD, we know that the previous priority in an EOI will always be
0xff (lowest priority).

Reviewed by:	nwhitehorn
Approved by:	re(rgrimes)
Differential Revision: https://reviews.freebsd.org/D17361
This commit is contained in:
jhibbits 2018-10-06 18:51:49 +00:00
parent 886d6e92be
commit 1a3c051aca
1 changed files with 3 additions and 11 deletions
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14
sys/powerpc/pseries/xics.c
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@ -381,17 +381,9 @@ xicp_dispatch(device_t dev, struct trapframe *tf)
}
xirr &= 0x00ffffff;
if (xirr == 0) { /* No more pending interrupts? */
if (regs)
bus_write_1(regs, 4, 0xff);
#ifdef POWERNV
else if (sc->xics_emu)
opal_call(OPAL_INT_SET_CPPR, 0xff);
#endif
else
phyp_hcall(H_CPPR, (uint64_t)0xff);
if (xirr == 0) /* No more pending interrupts? */
break;
}
if (xirr == XICP_IPI) { /* Magic number for IPIs */
xirr = MAX_XICP_IRQS; /* Map to FreeBSD magic */
@ -471,7 +463,7 @@ xicp_eoi(device_t dev, u_int irq)
if (irq == MAX_XICP_IRQS) /* Remap IPI interrupt to internal value */
irq = XICP_IPI;
xirr = irq | (XICP_PRIORITY << 24);
xirr = irq | (0xff << 24);
#ifdef POWERNV
if (mfmsr() & PSL_HV) {