MFp4: Status register bits
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@ -132,4 +132,18 @@
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#define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */
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#define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
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/* SSC_SR */
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#define SSC_SR_TXRDY (1u << 0)
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#define SSC_SR_TXEMPTY (1u << 1)
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#define SSC_SR_ENDTX (1u << 2)
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#define SSC_SR_TXBUFE (1u << 3)
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#define SSC_SR_RXRDY (1u << 4)
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#define SSC_SR_OVRUN (1u << 5)
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#define SSC_SR_ENDRX (1u << 6)
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#define SSC_SR_RXBUFF (1u << 7)
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#define SSC_SR_TXSYN (1u << 10)
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#define SSC_SR_RSSYN (1u << 11)
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#define SSC_SR_TXEN (1u << 16)
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#define SSC_SR_RXEN (1u << 17)
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#endif /* ARM_AT91_AT91_SSCREG_H */
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