MFC r277555, r277568:
Enable all sd device clocks on imx6. Add imx5/6 pinmux driver support for encoded input register configs.
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@ -95,7 +95,7 @@ ccm_init_gates(struct ccm_softc *sc)
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WR4(sc, CCM_CCGR3, 0x3ff00000); /* DDR memory controller */
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WR4(sc, CCM_CCGR4, 0x0000f300); /* pl301 bus crossbar */
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WR4(sc, CCM_CCGR5, 0x0f000000); /* uarts */
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WR4(sc, CCM_CCGR6, 0x000000cc); /* usdhc 1 & 3 */
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WR4(sc, CCM_CCGR6, 0x000000ff); /* usdhc 1-4 */
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}
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static int
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@ -117,10 +117,36 @@ WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val)
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bus_write_4(sc->mem_res, off, val);
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}
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static void
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iomux_configure_input(struct iomux_softc *sc, uint32_t reg, uint32_t val)
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{
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u_int select, mask, shift, width;
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/* If register and value are zero, there is nothing to configure. */
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if (reg == 0 && val == 0)
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return;
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/*
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* If the config value has 0xff in the high byte it is encoded:
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* 31 23 15 7 0
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* | 0xff | shift | width | select |
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* We need to mask out the old select value and OR in the new, using a
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* mask of the given width and shifting the values up by shift.
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*/
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if ((val & 0xff000000) == 0xff000000) {
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select = val & 0x000000ff;
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width = (val & 0x0000ff00) >> 8;
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shift = (val & 0x00ff0000) >> 16;
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mask = ((1u << width) - 1) << shift;
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val = (RD4(sc, reg) & ~mask) | (select << shift);
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}
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WR4(sc, reg, val);
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}
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static int
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iomux_configure_pins(device_t dev, phandle_t cfgxref)
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{
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struct iomux_softc * sc;
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struct iomux_softc *sc;
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struct pincfg *cfgtuples, *cfg;
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phandle_t cfgnode;
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int i, ntuples;
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@ -137,8 +163,7 @@ iomux_configure_pins(device_t dev, phandle_t cfgxref)
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for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) {
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sion = (cfg->padconf_val & PADCONF_SION) ? PADMUX_SION : 0;
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WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
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if (cfg->input_reg != 0)
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WR4(sc, cfg->input_reg, cfg->input_val);
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iomux_configure_input(sc, cfg->input_reg, cfg->input_val);
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if ((cfg->padconf_val & PADCONF_NONE) == 0)
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WR4(sc, cfg->padconf_reg, cfg->padconf_val);
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if (bootverbose) {
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