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Remove the local management of INTx as this is now taken care of by pci.

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Reviewed by:	jhb
MFC after:	3 days
This commit is contained in:
rnoland 2009-03-04 18:25:39 +00:00
parent 5e2ed35d24
commit 1c9035fabf
8 changed files with 0 additions and 32 deletions
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4
sys/dev/ata/chipsets/ata-acerlabs.c
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@ -113,10 +113,6 @@ ata_ali_chipinit(device_t dev)
if ((ctlr->chip->chipid == ATA_ALI_5288) &&
(ata_ahci_chipinit(dev) != ENXIO))
return 0;
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
break;
case ALI_NEW:

4
sys/dev/ata/chipsets/ata-ahci.c
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@ -135,10 +135,6 @@ ata_ahci_chipinit(device_t dev)
ctlr->suspend = ata_ahci_suspend;
ctlr->resume = ata_ahci_ctlr_reset;
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
/* announce we support the HW */
version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
device_printf(dev,

4
sys/dev/ata/chipsets/ata-intel.c
View File

@ -213,10 +213,6 @@ ata_intel_chipinit(device_t dev)
ctlr->setmode = ata_intel_sata_setmode;
else
ctlr->setmode = ata_sata_setmode;
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
}
return 0;
}

3
sys/dev/ata/chipsets/ata-marvell.c
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@ -212,9 +212,6 @@ ata_marvell_edma_chipinit(device_t dev)
ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
/*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
return 0;
}

5
sys/dev/ata/chipsets/ata-nvidia.c
View File

@ -183,11 +183,6 @@ ata_nvidia_chipinit(device_t dev)
/* enable device and PHY state change interrupts */
ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
}
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
}
ctlr->setmode = ata_sata_setmode;
}

4
sys/dev/ata/chipsets/ata-siliconimage.c
View File

@ -150,10 +150,6 @@ ata_sii_chipinit(device_t dev)
ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
DELAY(10000);
ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
break;
case SII_MEMIO:

4
sys/dev/ata/chipsets/ata-sis.c
View File

@ -189,10 +189,6 @@ ata_sis_chipinit(device_t dev)
ctlr->ch_attach = ata_sis_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_sis_reset;
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
}
ctlr->setmode = ata_sata_setmode;
return 0;

4
sys/dev/ata/chipsets/ata-via.c
View File

@ -143,10 +143,6 @@ ata_via_chipinit(device_t dev)
ctlr->ch_attach = ata_via_ch_attach;
ctlr->ch_detach = ata_via_ch_detach;
ctlr->reset = ata_via_reset;
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
}
if (ctlr->chip->cfg2 & VIABAR) {