Merge jmallett@'s n64 work into HEAD - changeset 6
PTE flag cleanup from http://svn.freebsd.org/base/user/jmallett/octeon - Rename PTE_xx flags to match their MIPS names - Use the new pte_set/test/clear macros uniformly, instead of a mixture of mips_pg_xxx(), pmap_pte_x() macros and direct access. - Remove unused macros and defines from pte.h and pmap.c Discussed on freebsd-mips@ Approved by: rrs(mentor), jmallett
This commit is contained in:
jchandra
parent
ff553ce010
commit
1cd81ae693
@ -32,7 +32,7 @@
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/*
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* TLB and PTE management. Most things operate within the context of
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* EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi
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* start with TLBHI_. PTE bits begin with PG_.
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* start with TLBHI_. PTE bits begin with PTE_.
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*
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* Note that we use the same size VM and TLB pages.
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*/
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@ -63,7 +63,7 @@
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#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
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#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK)
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#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
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/*
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* VPN for EntryHi register. Upper two bits select user, supervisor,
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* or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to
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@ -76,54 +76,57 @@
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#define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
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#ifndef _LOCORE
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typedef unsigned int pt_entry_t;
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typedef pt_entry_t *pd_entry_t;
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typedef uint32_t pt_entry_t;
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typedef pt_entry_t *pd_entry_t;
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#endif
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#define PDESIZE sizeof(pd_entry_t) /* for assembly files */
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#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
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#define PT_ENTRY_NULL ((pt_entry_t *) 0)
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#define PTE_WIRED 0x80000000 /* SW */
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#define PTE_W PTE_WIRED
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#define PTE_RO 0x40000000 /* SW */
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#define PTE_G 0x00000001 /* HW */
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#define PTE_V 0x00000002
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/*#define PTE_NV 0x00000000 Not Used */
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#define PTE_M 0x00000004
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#define PTE_RW PTE_M
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#define PTE_ODDPG 0x00001000
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/*#define PG_ATTR 0x0000003f Not Used */
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#define PTE_UNCACHED 0x00000010
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#ifdef CPU_SB1
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#define PTE_CACHE 0x00000028 /* cacheable coherent */
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/*
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* TLB flags managed in hardware:
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* C: Cache attribute.
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* D: Dirty bit. This means a page is writable. It is not
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* set at first, and a write is trapped, and the dirty
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* bit is set. See also PTE_RO.
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* V: Valid bit. Obvious, isn't it?
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* G: Global bit. This means that this mapping is present
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* in EVERY address space, and to ignore the ASID when
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* it is matched.
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*/
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#define PTE_C(attr) ((attr & 0x07) << 3)
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#define PTE_C_UNCACHED (PTE_C(0x02))
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/*
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* The preferred cache attribute for cacheable pages, this can be
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* implementation dependent. We will use the standard value 0x3 as
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* default.
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*/
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#if defined(CPU_SB1)
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#define PTE_C_CACHE (PTE_C(0x05))
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#else
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#define PTE_CACHE 0x00000018
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#define PTE_C_CACHE (PTE_C(0x03))
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#endif
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/*#define PG_CACHEMODE 0x00000038 Not Used*/
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#define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */
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#define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */
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#define PTE_CWPAGE (PTE_V | PTE_CACHE) /* Not wr-prot but clean */
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#define PTE_IOPAGE (PTE_G | PTE_V | PTE_M | PTE_UNCACHED)
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#define PTE_FRAME 0x3fffffc0
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#define PTE_HVPN 0xffffe000 /* Hardware page no mask */
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#define PTE_ASID 0x000000ff /* Address space ID */
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#define PTE_D 0x04
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#define PTE_V 0x02
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#define PTE_G 0x01
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/*
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* VM flags managed in software:
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* RO: Read only. Never set PTE_D on this page, and don't
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* listen to requests to write to it.
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* W: Wired. ???
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*/
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#define PTE_RO (0x01 << TLBLO_SWBITS_SHIFT)
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#define PTE_W (0x02 << TLBLO_SWBITS_SHIFT)
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/* User virtual to pte offset in page table */
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#define vad_to_pte_offset(adr) (((adr) >> PAGE_SHIFT) & (NPTEPG -1))
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#define mips_pg_v(entry) ((entry) & PTE_V)
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#define mips_pg_wired(entry) ((entry) & PTE_WIRED)
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#define mips_pg_m_bit() (PTE_M)
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#define mips_pg_rw_bit() (PTE_M)
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#define mips_pg_ro_bit() (PTE_RO)
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#define mips_pg_ropage_bit() (PTE_ROPAGE)
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#define mips_pg_rwpage_bit() (PTE_RWPAGE)
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#define mips_pg_cwpage_bit() (PTE_CWPAGE)
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#define mips_pg_global_bit() (PTE_G)
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#define mips_pg_wired_bit() (PTE_WIRED)
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/*
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* PTE management functions for bits defined above.
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*
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* XXX Can make these atomics, but some users of them are using PTEs in local
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* registers and such and don't need the overhead.
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*/
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#define pte_clear(pte, bit) (*(pte) &= ~(bit))
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#define pte_set(pte, bit) (*(pte) |= (bit))
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#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit))
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#endif /* !_MACHINE_PTE_H_ */
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@ -32,9 +32,7 @@
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#include <machine/pte.h>
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/* Memory attributes. */
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#define VM_MEMATTR_UNCACHED ((vm_memattr_t)PTE_UNCACHED)
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#define VM_MEMATTR_CACHEABLE_NONCOHERENT ((vm_memattr_t)PTE_CACHE)
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#define VM_MEMATTR_DEFAULT VM_MEMATTR_CACHEABLE_NONCOHERENT
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#define VM_MEMATTR_UNCACHED ((vm_memattr_t)PTE_C_UNCACHED)
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#define VM_MEMATTR_DEFAULT ((vm_memattr_t)PTE_C_CACHE)
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#endif /* !_MACHINE_VM_H_ */
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@ -421,7 +421,7 @@ mips_pcpu_tlb_init(struct pcpu *pcpu)
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* We use a wired tlb index to do this one-time mapping.
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*/
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pa = vtophys(pcpu);
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pte = PTE_RW | PTE_V | PTE_G | PTE_CACHE;
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pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE;
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tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
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TLBLO_PA_TO_PFN(pa) | pte,
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TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
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@ -68,7 +68,6 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include "opt_msgbuf.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -120,22 +119,13 @@ __FBSDID("$FreeBSD$");
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/*
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* Get PDEs and PTEs for user/kernel address space
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*/
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#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT]))
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#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT]))
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#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT])
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#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0)
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#define pmap_pde_v(pte) ((*(int *)pte) != 0)
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#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0)
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#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0)
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#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W))
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#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
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#define MIPS_SEGSIZE (1L << SEGSHIFT)
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#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1))
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#define pmap_TLB_invalidate_all() MIPS_TBIAP()
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#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT))
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#define is_kernel_pmap(x) ((x) == kernel_pmap)
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#define vad_to_pte_offset(adr) (((adr) >> PAGE_SHIFT) & (NPTEPG -1))
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struct pmap kernel_pmap_store;
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pd_entry_t *kernel_segmap;
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@ -172,9 +162,10 @@ static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
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static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va);
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static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
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static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
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static boolean_t pmap_testbit(vm_page_t m, int bit);
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static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
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vm_offset_t va, vm_page_t m);
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static __inline void
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pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
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static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
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@ -218,10 +209,10 @@ static struct local_sysmaps sysmap_lmem[MAXCPU];
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sysm = &sysmap_lmem[cpu]; \
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va = sysm->base; \
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npte = TLBLO_PA_TO_PFN(phys) | \
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PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \
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PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; \
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pte = pmap_pte(kernel_pmap, va); \
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*pte = npte; \
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sysm->valid1 = 1;
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sysm->valid1 = 1
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#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \
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int cpu; \
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@ -234,11 +225,11 @@ static struct local_sysmaps sysmap_lmem[MAXCPU];
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va1 = sysm->base; \
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va2 = sysm->base + PAGE_SIZE; \
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npte = TLBLO_PA_TO_PFN(phys1) | \
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PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \
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PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; \
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pte = pmap_pte(kernel_pmap, va1); \
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*pte = npte; \
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npte = TLBLO_PA_TO_PFN(phys2) | \
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PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \
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PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; \
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pte = pmap_pte(kernel_pmap, va2); \
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*pte = npte; \
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sysm->valid1 = 1; \
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@ -543,7 +534,7 @@ pmap_init(void)
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static int
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pmap_nw_modified(pt_entry_t pte)
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{
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if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO))
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if ((pte & (PTE_D | PTE_RO)) == (PTE_D | PTE_RO))
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return (1);
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else
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return (0);
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@ -694,8 +685,8 @@ pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
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PMAP_LOCK(pmap);
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retry:
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pte = *pmap_pte(pmap, va);
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if (pte != 0 && pmap_pte_v(&pte) &&
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((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) {
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if (pte != 0 && pte_test(&pte, PTE_V) &&
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(pte_test(&pte, PTE_D) || (prot & VM_PROT_WRITE) == 0)) {
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if (vm_page_pa_tryrelock(pmap, TLBLO_PTE_TO_PA(pte), &pa))
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goto retry;
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@ -717,18 +708,18 @@ retry:
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/* PMAP_INLINE */ void
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pmap_kenter(vm_offset_t va, vm_paddr_t pa)
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{
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register pt_entry_t *pte;
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pt_entry_t npte, opte;
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pt_entry_t *pte;
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pt_entry_t opte, npte;
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#ifdef PMAP_DEBUG
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printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa);
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printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
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#endif
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npte = TLBLO_PA_TO_PFN(pa) | PTE_RW | PTE_V | PTE_G | PTE_W;
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npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | PTE_W;
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if (is_cacheable_mem(pa))
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npte |= PTE_CACHE;
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npte |= PTE_C_CACHE;
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else
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npte |= PTE_UNCACHED;
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npte |= PTE_C_UNCACHED;
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pte = pmap_pte(kernel_pmap, va);
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opte = *pte;
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@ -743,7 +734,7 @@ pmap_kenter(vm_offset_t va, vm_paddr_t pa)
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/* PMAP_INLINE */ void
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pmap_kremove(vm_offset_t va)
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{
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register pt_entry_t *pte;
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pt_entry_t *pte;
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/*
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* Write back all caches from the page being destroyed
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@ -1305,11 +1296,11 @@ retry:
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oldpte = loadandclear((u_int *)pte);
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if (is_kernel_pmap(pmap))
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*pte = PTE_G;
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KASSERT((oldpte & PTE_W) == 0,
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KASSERT(!pte_test(&oldpte, PTE_W),
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("wired pte for unwired page"));
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if (m->md.pv_flags & PV_TABLE_REF)
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vm_page_flag_set(m, PG_REFERENCED);
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if (oldpte & PTE_M)
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if (pte_test(&oldpte, PTE_D))
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vm_page_dirty(m);
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pmap_invalidate_page(pmap, va);
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TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist);
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@ -1449,7 +1440,7 @@ pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va)
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if (is_kernel_pmap(pmap))
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*ptq = PTE_G;
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if (oldpte & PTE_W)
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if (pte_test(&oldpte, PTE_W))
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pmap->pm_stats.wired_count -= 1;
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pmap->pm_stats.resident_count -= 1;
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@ -1457,7 +1448,7 @@ pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va)
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if (page_is_managed(pa)) {
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m = PHYS_TO_VM_PAGE(pa);
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if (oldpte & PTE_M) {
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if (pte_test(&oldpte, PTE_D)) {
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#if defined(PMAP_DIAGNOSTIC)
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if (pmap_nw_modified(oldpte)) {
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printf(
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@ -1482,7 +1473,7 @@ pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va)
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static void
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pmap_remove_page(struct pmap *pmap, vm_offset_t va)
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{
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register pt_entry_t *ptq;
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pt_entry_t *ptq;
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mtx_assert(&vm_page_queue_mtx, MA_OWNED);
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PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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@ -1491,7 +1482,7 @@ pmap_remove_page(struct pmap *pmap, vm_offset_t va)
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/*
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* if there is no pte for this address, just skip it!!!
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*/
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if (!ptq || !pmap_pte_v(ptq)) {
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if (!ptq || !pte_test(ptq, PTE_V)) {
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return;
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}
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@ -1567,8 +1558,8 @@ out:
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void
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pmap_remove_all(vm_page_t m)
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{
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register pv_entry_t pv;
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register pt_entry_t *pte, tpte;
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pv_entry_t pv;
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pt_entry_t *pte, tpte;
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KASSERT((m->flags & PG_FICTITIOUS) == 0,
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("pmap_remove_all: page %p is fictitious", m));
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@ -1595,13 +1586,13 @@ pmap_remove_all(vm_page_t m)
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if (is_kernel_pmap(pv->pv_pmap))
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*pte = PTE_G;
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if (tpte & PTE_W)
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if (pte_test(&tpte, PTE_W))
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pv->pv_pmap->pm_stats.wired_count--;
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/*
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* Update the vm_page_t clean and reference bits.
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*/
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if (tpte & PTE_M) {
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if (pte_test(&tpte, PTE_D)) {
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#if defined(PMAP_DIAGNOSTIC)
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if (pmap_nw_modified(tpte)) {
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printf(
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@ -1663,7 +1654,7 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
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* If pte is invalid, skip this page
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*/
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pte = pmap_pte(pmap, sva);
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if (!pmap_pte_v(pte)) {
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if (!pte_test(pte, PTE_V)) {
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sva += PAGE_SIZE;
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continue;
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}
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@ -1671,12 +1662,13 @@ retry:
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obits = pbits = *pte;
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pa = TLBLO_PTE_TO_PA(pbits);
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if (page_is_managed(pa) && (pbits & PTE_M) != 0) {
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if (page_is_managed(pa) && pte_test(&pbits, PTE_D)) {
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m = PHYS_TO_VM_PAGE(pa);
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vm_page_dirty(m);
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m->md.pv_flags &= ~PV_TABLE_MOD;
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}
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pbits = (pbits & ~PTE_M) | PTE_RO;
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pte_clear(&pbits, PTE_D);
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pte_set(&pbits, PTE_RO);
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|
||||
if (pbits != *pte) {
|
||||
if (!atomic_cmpset_int((u_int *)pte, obits, pbits))
|
||||
@ -1706,7 +1698,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
|
||||
vm_prot_t prot, boolean_t wired)
|
||||
{
|
||||
vm_offset_t pa, opa;
|
||||
register pt_entry_t *pte;
|
||||
pt_entry_t *pte;
|
||||
pt_entry_t origpte, newpte;
|
||||
pv_entry_t pv;
|
||||
vm_page_t mpte, om;
|
||||
@ -1750,16 +1742,16 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
|
||||
/*
|
||||
* Mapping has not changed, must be protection or wiring change.
|
||||
*/
|
||||
if ((origpte & PTE_V) && (opa == pa)) {
|
||||
if (pte_test(&origpte, PTE_V) && opa == pa) {
|
||||
/*
|
||||
* Wiring change, just update stats. We don't worry about
|
||||
* wiring PT pages as they remain resident as long as there
|
||||
* are valid mappings in them. Hence, if a user page is
|
||||
* wired, the PT page will be also.
|
||||
*/
|
||||
if (wired && ((origpte & PTE_W) == 0))
|
||||
if (wired && !pte_test(&origpte, PTE_W))
|
||||
pmap->pm_stats.wired_count++;
|
||||
else if (!wired && (origpte & PTE_W))
|
||||
else if (!wired && pte_test(&origpte, PTE_W))
|
||||
pmap->pm_stats.wired_count--;
|
||||
|
||||
#if defined(PMAP_DIAGNOSTIC)
|
||||
@ -1789,7 +1781,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
|
||||
* handle validating new mapping.
|
||||
*/
|
||||
if (opa) {
|
||||
if (origpte & PTE_W)
|
||||
if (pte_test(&origpte, PTE_W))
|
||||
pmap->pm_stats.wired_count--;
|
||||
|
||||
if (page_is_managed(opa)) {
|
||||
@ -1837,7 +1829,7 @@ validate:
|
||||
rw = init_pte_prot(va, m, prot);
|
||||
|
||||
#ifdef PMAP_DEBUG
|
||||
printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa);
|
||||
printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
|
||||
#endif
|
||||
/*
|
||||
* Now validate mapping with desired protection/wiring.
|
||||
@ -1845,23 +1837,22 @@ validate:
|
||||
newpte = TLBLO_PA_TO_PFN(pa) | rw | PTE_V;
|
||||
|
||||
if (is_cacheable_mem(pa))
|
||||
newpte |= PTE_CACHE;
|
||||
newpte |= PTE_C_CACHE;
|
||||
else
|
||||
newpte |= PTE_UNCACHED;
|
||||
newpte |= PTE_C_UNCACHED;
|
||||
|
||||
if (wired)
|
||||
newpte |= PTE_W;
|
||||
|
||||
if (is_kernel_pmap(pmap)) {
|
||||
if (is_kernel_pmap(pmap))
|
||||
newpte |= PTE_G;
|
||||
}
|
||||
|
||||
/*
|
||||
* if the mapping or permission bits are different, we need to
|
||||
* update the pte.
|
||||
*/
|
||||
if (origpte != newpte) {
|
||||
if (origpte & PTE_V) {
|
||||
if (pte_test(&origpte, PTE_V)) {
|
||||
*pte = newpte;
|
||||
if (page_is_managed(opa) && (opa != pa)) {
|
||||
if (om->md.pv_flags & PV_TABLE_REF)
|
||||
@ -1869,8 +1860,8 @@ validate:
|
||||
om->md.pv_flags &=
|
||||
~(PV_TABLE_REF | PV_TABLE_MOD);
|
||||
}
|
||||
if (origpte & PTE_M) {
|
||||
KASSERT((origpte & PTE_RW),
|
||||
if (pte_test(&origpte, PTE_D)) {
|
||||
KASSERT(!pte_test(&origpte, PTE_RO),
|
||||
("pmap_enter: modified page not writable:"
|
||||
" va: %p, pte: 0x%x", (void *)va, origpte));
|
||||
if (page_is_managed(opa))
|
||||
@ -1978,7 +1969,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
|
||||
}
|
||||
|
||||
pte = pmap_pte(pmap, va);
|
||||
if (pmap_pte_v(pte)) {
|
||||
if (pte_test(pte, PTE_V)) {
|
||||
if (mpte != NULL) {
|
||||
mpte->wire_count--;
|
||||
mpte = NULL;
|
||||
@ -2011,9 +2002,9 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
|
||||
*pte = TLBLO_PA_TO_PFN(pa) | PTE_V;
|
||||
|
||||
if (is_cacheable_mem(pa))
|
||||
*pte |= PTE_CACHE;
|
||||
*pte |= PTE_C_CACHE;
|
||||
else
|
||||
*pte |= PTE_UNCACHED;
|
||||
*pte |= PTE_C_UNCACHED;
|
||||
|
||||
if (is_kernel_pmap(pmap))
|
||||
*pte |= PTE_G;
|
||||
@ -2061,7 +2052,7 @@ pmap_kenter_temporary(vm_paddr_t pa, int i)
|
||||
cpu = PCPU_GET(cpuid);
|
||||
sysm = &sysmap_lmem[cpu];
|
||||
/* Since this is for the debugger, no locks or any other fun */
|
||||
npte = TLBLO_PA_TO_PFN(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE;
|
||||
npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE;
|
||||
pte = pmap_pte(kernel_pmap, sysm->base);
|
||||
*pte = npte;
|
||||
sysm->valid1 = 1;
|
||||
@ -2160,7 +2151,7 @@ pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
|
||||
void
|
||||
pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
|
||||
{
|
||||
register pt_entry_t *pte;
|
||||
pt_entry_t *pte;
|
||||
|
||||
if (pmap == NULL)
|
||||
return;
|
||||
@ -2168,16 +2159,19 @@ pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
|
||||
PMAP_LOCK(pmap);
|
||||
pte = pmap_pte(pmap, va);
|
||||
|
||||
if (wired && !pmap_pte_w(pte))
|
||||
if (wired && !pte_test(pte, PTE_W))
|
||||
pmap->pm_stats.wired_count++;
|
||||
else if (!wired && pmap_pte_w(pte))
|
||||
else if (!wired && pte_test(pte, PTE_W))
|
||||
pmap->pm_stats.wired_count--;
|
||||
|
||||
/*
|
||||
* Wiring is not a hardware characteristic so there is no need to
|
||||
* invalidate TLB.
|
||||
*/
|
||||
pmap_pte_set_w(pte, wired);
|
||||
if (wired)
|
||||
pte_set(pte, PTE_W);
|
||||
else
|
||||
pte_clear(pte, PTE_W);
|
||||
PMAP_UNLOCK(pmap);
|
||||
}
|
||||
|
||||
@ -2363,14 +2357,14 @@ pmap_remove_pages(pmap_t pmap)
|
||||
for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
|
||||
|
||||
pte = pmap_pte(pv->pv_pmap, pv->pv_va);
|
||||
if (!pmap_pte_v(pte))
|
||||
if (!pte_test(pte, PTE_V))
|
||||
panic("pmap_remove_pages: page on pm_pvlist has no pte\n");
|
||||
tpte = *pte;
|
||||
|
||||
/*
|
||||
* We cannot remove wired pages from a process' mapping at this time
|
||||
*/
|
||||
if (tpte & PTE_W) {
|
||||
if (pte_test(&tpte, PTE_W)) {
|
||||
npv = TAILQ_NEXT(pv, pv_plist);
|
||||
continue;
|
||||
}
|
||||
@ -2385,7 +2379,7 @@ pmap_remove_pages(pmap_t pmap)
|
||||
/*
|
||||
* Update the vm_page_t clean and reference bits.
|
||||
*/
|
||||
if (tpte & PTE_M) {
|
||||
if (pte_test(&tpte, PTE_D)) {
|
||||
vm_page_dirty(m);
|
||||
}
|
||||
npv = TAILQ_NEXT(pv, pv_plist);
|
||||
@ -2433,7 +2427,7 @@ pmap_testbit(vm_page_t m, int bit)
|
||||
#endif
|
||||
PMAP_LOCK(pv->pv_pmap);
|
||||
pte = pmap_pte(pv->pv_pmap, pv->pv_va);
|
||||
rv = (*pte & bit) != 0;
|
||||
rv = pte_test(pte, bit);
|
||||
PMAP_UNLOCK(pv->pv_pmap);
|
||||
if (rv)
|
||||
break;
|
||||
@ -2442,13 +2436,13 @@ pmap_testbit(vm_page_t m, int bit)
|
||||
}
|
||||
|
||||
/*
|
||||
* this routine is used to modify bits in ptes
|
||||
* this routine is used to clear dirty bits in ptes
|
||||
*/
|
||||
static __inline void
|
||||
pmap_changebit(vm_page_t m, int bit, boolean_t setem)
|
||||
{
|
||||
register pv_entry_t pv;
|
||||
register pt_entry_t *pte;
|
||||
pv_entry_t pv;
|
||||
pt_entry_t *pte;
|
||||
|
||||
if (m->flags & PG_FICTITIOUS)
|
||||
return;
|
||||
@ -2476,12 +2470,11 @@ pmap_changebit(vm_page_t m, int bit, boolean_t setem)
|
||||
vm_offset_t pbits = *(vm_offset_t *)pte;
|
||||
|
||||
if (pbits & bit) {
|
||||
if (bit == PTE_RW) {
|
||||
if (pbits & PTE_M) {
|
||||
if (bit == PTE_D) {
|
||||
if (pbits & PTE_D) {
|
||||
vm_page_dirty(m);
|
||||
}
|
||||
*(int *)pte = (pbits & ~(PTE_M | PTE_RW)) |
|
||||
PTE_RO;
|
||||
*(int *)pte = (pbits & ~PTE_D) | PTE_RO;
|
||||
} else {
|
||||
*(int *)pte = pbits & ~bit;
|
||||
}
|
||||
@ -2490,7 +2483,7 @@ pmap_changebit(vm_page_t m, int bit, boolean_t setem)
|
||||
}
|
||||
PMAP_UNLOCK(pv->pv_pmap);
|
||||
}
|
||||
if (!setem && bit == PTE_RW)
|
||||
if (!setem && bit == PTE_D)
|
||||
vm_page_flag_clear(m, PG_WRITEABLE);
|
||||
}
|
||||
|
||||
@ -2547,8 +2540,7 @@ pmap_remove_write(vm_page_t m)
|
||||
for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) {
|
||||
npv = TAILQ_NEXT(pv, pv_plist);
|
||||
pte = pmap_pte(pv->pv_pmap, pv->pv_va);
|
||||
|
||||
if ((pte == NULL) || !mips_pg_v(*pte))
|
||||
if (pte == NULL || !pte_test(pte, PTE_V))
|
||||
panic("page on pm_pvlist has no pte\n");
|
||||
|
||||
va = pv->pv_va;
|
||||
@ -2596,7 +2588,7 @@ pmap_is_modified(vm_page_t m)
|
||||
/*
|
||||
* If the page is not VPO_BUSY, then PG_WRITEABLE cannot be
|
||||
* concurrently set while the object is locked. Thus, if PG_WRITEABLE
|
||||
* is clear, no PTEs can have PTE_M set.
|
||||
* is clear, no PTEs can have PTE_D set.
|
||||
*/
|
||||
VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
|
||||
if ((m->oflags & VPO_BUSY) == 0 &&
|
||||
@ -2606,7 +2598,7 @@ pmap_is_modified(vm_page_t m)
|
||||
if (m->md.pv_flags & PV_TABLE_MOD)
|
||||
rv = TRUE;
|
||||
else
|
||||
rv = pmap_testbit(m, PTE_M);
|
||||
rv = pmap_testbit(m, PTE_D);
|
||||
vm_page_unlock_queues();
|
||||
return (rv);
|
||||
}
|
||||
@ -2649,7 +2641,7 @@ pmap_clear_modify(vm_page_t m)
|
||||
("pmap_clear_modify: page %p is busy", m));
|
||||
|
||||
/*
|
||||
* If the page is not PG_WRITEABLE, then no PTEs can have PTE_M set.
|
||||
* If the page is not PG_WRITEABLE, then no PTEs can have PTE_D set.
|
||||
* If the object containing the page is locked and the page is not
|
||||
* VPO_BUSY, then PG_WRITEABLE cannot be concurrently set.
|
||||
*/
|
||||
@ -2657,7 +2649,7 @@ pmap_clear_modify(vm_page_t m)
|
||||
return;
|
||||
vm_page_lock_queues();
|
||||
if (m->md.pv_flags & PV_TABLE_MOD) {
|
||||
pmap_changebit(m, PTE_M, FALSE);
|
||||
pmap_changebit(m, PTE_D, FALSE);
|
||||
m->md.pv_flags &= ~PV_TABLE_MOD;
|
||||
}
|
||||
vm_page_unlock_queues();
|
||||
@ -2776,12 +2768,12 @@ pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
|
||||
retry:
|
||||
ptep = pmap_pte(pmap, addr);
|
||||
pte = (ptep != NULL) ? *ptep : 0;
|
||||
if (!mips_pg_v(pte)) {
|
||||
if (!pte_test(&pte, PTE_V)) {
|
||||
val = 0;
|
||||
goto out;
|
||||
}
|
||||
val = MINCORE_INCORE;
|
||||
if ((pte & PTE_M) != 0)
|
||||
if (pte_test(&pte, PTE_D))
|
||||
val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
|
||||
pa = TLBLO_PTE_TO_PA(pte);
|
||||
managed = page_is_managed(pa);
|
||||
@ -2907,13 +2899,13 @@ pmap_pid_dump(int pid)
|
||||
unsigned base = i << SEGSHIFT;
|
||||
|
||||
pde = &pmap->pm_segtab[i];
|
||||
if (pde && pmap_pde_v(pde)) {
|
||||
if (pde && *pde != 0) {
|
||||
for (j = 0; j < 1024; j++) {
|
||||
vm_offset_t va = base +
|
||||
(j << PAGE_SHIFT);
|
||||
|
||||
pte = pmap_pte(pmap, va);
|
||||
if (pte && pmap_pte_v(pte)) {
|
||||
if (pte && pte_test(pte, PTE_V)) {
|
||||
vm_offset_t pa;
|
||||
vm_page_t m;
|
||||
|
||||
@ -3050,16 +3042,16 @@ init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot)
|
||||
int rw;
|
||||
|
||||
if (!(prot & VM_PROT_WRITE))
|
||||
rw = PTE_ROPAGE;
|
||||
rw = PTE_V | PTE_RO | PTE_C_CACHE;
|
||||
else if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) {
|
||||
if ((m->md.pv_flags & PV_TABLE_MOD) != 0)
|
||||
rw = PTE_RWPAGE;
|
||||
rw = PTE_V | PTE_D | PTE_C_CACHE;
|
||||
else
|
||||
rw = PTE_CWPAGE;
|
||||
rw = PTE_V | PTE_C_CACHE;
|
||||
vm_page_flag_set(m, PG_WRITEABLE);
|
||||
} else
|
||||
/* Needn't emulate a modified bit for unmanaged pages. */
|
||||
rw = PTE_RWPAGE;
|
||||
rw = PTE_V | PTE_D | PTE_C_CACHE;
|
||||
return (rw);
|
||||
}
|
||||
|
||||
|
||||
@ -327,7 +327,7 @@ trap(struct trapframe *trapframe)
|
||||
#ifdef SMP
|
||||
printf("cpuid = %d\n", PCPU_GET(cpuid));
|
||||
#endif
|
||||
MachTLBGetPID(pid);
|
||||
pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
|
||||
printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
|
||||
(intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
|
||||
(intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
|
||||
@ -378,23 +378,23 @@ trap(struct trapframe *trapframe)
|
||||
panic("trap: ktlbmod: can't find PTE");
|
||||
#ifdef SMP
|
||||
/* It is possible that some other CPU changed m-bit */
|
||||
if (!mips_pg_v(*pte) || (*pte & mips_pg_m_bit())) {
|
||||
if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
|
||||
pmap_update_page(kernel_pmap,
|
||||
trapframe->badvaddr, *pte);
|
||||
PMAP_UNLOCK(kernel_pmap);
|
||||
return (trapframe->pc);
|
||||
}
|
||||
#else
|
||||
if (!mips_pg_v(*pte) || (*pte & mips_pg_m_bit()))
|
||||
if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
|
||||
panic("trap: ktlbmod: invalid pte");
|
||||
#endif
|
||||
if (*pte & mips_pg_ro_bit()) {
|
||||
if (pte_test(pte, PTE_RO)) {
|
||||
/* write to read only page in the kernel */
|
||||
ftype = VM_PROT_WRITE;
|
||||
PMAP_UNLOCK(kernel_pmap);
|
||||
goto kernel_fault;
|
||||
}
|
||||
*pte |= mips_pg_m_bit();
|
||||
pte_set(pte, PTE_D);
|
||||
pmap_update_page(kernel_pmap, trapframe->badvaddr, *pte);
|
||||
pa = TLBLO_PTE_TO_PA(*pte);
|
||||
if (!page_is_managed(pa))
|
||||
@ -417,23 +417,23 @@ trap(struct trapframe *trapframe)
|
||||
panic("trap: utlbmod: can't find PTE");
|
||||
#ifdef SMP
|
||||
/* It is possible that some other CPU changed m-bit */
|
||||
if (!mips_pg_v(*pte) || (*pte & mips_pg_m_bit())) {
|
||||
if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
|
||||
pmap_update_page(pmap, trapframe->badvaddr, *pte);
|
||||
PMAP_UNLOCK(pmap);
|
||||
goto out;
|
||||
}
|
||||
#else
|
||||
if (!mips_pg_v(*pte) || (*pte & mips_pg_m_bit()))
|
||||
if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
|
||||
panic("trap: utlbmod: invalid pte");
|
||||
#endif
|
||||
|
||||
if (*pte & mips_pg_ro_bit()) {
|
||||
if (pte_test(pte, PTE_RO)) {
|
||||
/* write to read only page */
|
||||
ftype = VM_PROT_WRITE;
|
||||
PMAP_UNLOCK(pmap);
|
||||
goto dofault;
|
||||
}
|
||||
*pte |= mips_pg_m_bit();
|
||||
pte_set(pte, PTE_D);
|
||||
pmap_update_page(pmap, trapframe->badvaddr, *pte);
|
||||
pa = TLBLO_PTE_TO_PA(*pte);
|
||||
if (!page_is_managed(pa))
|
||||
|
||||
@ -219,7 +219,7 @@ cpu_thread_swapin(struct thread *td)
|
||||
*/
|
||||
for (i = 0; i < KSTACK_PAGES; i++) {
|
||||
pte = pmap_pte(kernel_pmap, td->td_kstack + i * PAGE_SIZE);
|
||||
td->td_md.md_upte[i] = *pte & ~(PTE_RO|PTE_WIRED);
|
||||
td->td_md.md_upte[i] = *pte & ~TLBLO_SWBITS_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
@ -241,7 +241,7 @@ cpu_thread_alloc(struct thread *td)
|
||||
|
||||
for (i = 0; i < KSTACK_PAGES; i++) {
|
||||
pte = pmap_pte(kernel_pmap, td->td_kstack + i * PAGE_SIZE);
|
||||
td->td_md.md_upte[i] = *pte & ~(PTE_RO|PTE_WIRED);
|
||||
td->td_md.md_upte[i] = *pte & ~TLBLO_SWBITS_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user