Add driver for Xilinx AXI Quad SPI device. The device was found in
lowRISC hardware. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
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sys/dev/xilinx/axi_quad_spi.c
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sys/dev/xilinx/axi_quad_spi.c
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Xilinx AXI_QUAD_SPI
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include "spibus_if.h"
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#define READ4(_sc, _reg) \
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bus_space_read_4(_sc->bst, _sc->bsh, _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
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#define SPI_SRR 0x40 /* Software reset register */
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#define SRR_RESET 0x0A /* The only reset value */
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#define SPI_CR 0x60 /* Control register */
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#define CR_LSB_FIRST (1 << 9) /* LSB first */
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#define CR_MASTER_TI (1 << 8) /* Master Transaction Inhibit */
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#define CR_MSS (1 << 7) /* Manual Slave Select */
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#define CR_RST_RX (1 << 6) /* RX FIFO Reset */
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#define CR_RST_TX (1 << 5) /* TX FIFO Reset */
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#define CR_CPHA (1 << 4) /* Clock phase */
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#define CR_CPOL (1 << 3) /* Clock polarity */
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#define CR_MASTER (1 << 2) /* Master (SPI master mode) */
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#define CR_SPE (1 << 1) /* SPI system enable */
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#define CR_LOOP (1 << 0) /* Local loopback mode */
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#define SPI_SR 0x64 /* Status register */
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#define SR_TX_FULL (1 << 3) /* Transmit full */
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#define SR_TX_EMPTY (1 << 2) /* Transmit empty */
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#define SR_RX_FULL (1 << 1) /* Receive full */
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#define SR_RX_EMPTY (1 << 0) /* Receive empty */
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#define SPI_DTR 0x68 /* Data transmit register */
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#define SPI_DRR 0x6C /* Data receive register */
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#define SPI_SSR 0x70 /* Slave select register */
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#define SPI_TFOR 0x74 /* Transmit FIFO Occupancy Register */
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#define SPI_RFOR 0x78 /* Receive FIFO Occupancy Register */
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#define SPI_DGIER 0x1C /* Device global interrupt enable register */
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#define SPI_IPISR 0x20 /* IP interrupt status register */
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#define SPI_IPIER 0x28 /* IP interrupt enable register */
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struct spi_softc {
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struct resource *res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih;
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};
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static struct resource_spec spi_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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spi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "xlnx,xps-spi-3.2"))
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return (ENXIO);
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device_set_desc(dev, "Xilinx Quad SPI");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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spi_chip_select(device_t dev, device_t child)
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{
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struct spi_softc *sc;
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uint32_t cs;
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sc = device_get_softc(dev);
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spibus_get_cs(child, &cs);
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WRITE4(sc, SPI_SSR, ~(1 << cs));
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return (0);
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}
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static int
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spi_chip_deselect(device_t dev, device_t child)
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{
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struct spi_softc *sc;
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sc = device_get_softc(dev);
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WRITE4(sc, SPI_SSR, ~0);
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return (0);
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}
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static int
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spi_attach(device_t dev)
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{
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struct spi_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, spi_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Reset */
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WRITE4(sc, SPI_SRR, SRR_RESET);
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DELAY(1000);
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reg = (CR_MASTER | CR_MSS | CR_RST_RX | CR_RST_TX);
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WRITE4(sc, SPI_CR, reg);
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WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */
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reg = (CR_MASTER | CR_MSS | CR_SPE);
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WRITE4(sc, SPI_CR, reg);
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device_add_child(dev, "spibus", 0);
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return (bus_generic_attach(dev));
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}
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static int
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spi_txrx(struct spi_softc *sc, uint8_t *out_buf,
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uint8_t *in_buf, int bufsz, int cs)
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{
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uint32_t data;
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uint32_t i;
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for (i = 0; i < bufsz; i++) {
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WRITE4(sc, SPI_DTR, out_buf[i]);
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while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY))
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continue;
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data = READ4(sc, SPI_DRR);
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if (in_buf)
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in_buf[i] = (data & 0xff);
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}
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return (0);
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}
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static int
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spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct spi_softc *sc;
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uint32_t cs;
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sc = device_get_softc(dev);
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("%s: TX/RX command sizes should be equal", __func__));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("%s: TX/RX data sizes should be equal", __func__));
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/* get the proper chip select */
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spibus_get_cs(child, &cs);
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/* Command */
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spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs);
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/* Data */
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spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs);
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return (0);
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}
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static device_method_t spi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, spi_probe),
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DEVMETHOD(device_attach, spi_attach),
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/* SPI interface */
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DEVMETHOD(spibus_transfer, spi_transfer),
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DEVMETHOD(spibus_chip_select, spi_chip_select),
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DEVMETHOD(spibus_chip_deselect, spi_chip_deselect),
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DEVMETHOD_END
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};
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static driver_t spi_driver = {
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"spi",
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spi_methods,
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sizeof(struct spi_softc),
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};
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static devclass_t spi_devclass;
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DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0);
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