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ig4(4): Fix SDA HOLD time set too low on Skylake controllers

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Execution of "Soft reset" command (IG4_REG_RESETS_SKL) at controller init
stage sets SDA_HOLD register value to 0x0001 which is often too low for
normal operation.

Set SDA_HOLD back to 28 after reset to restore controller functionality.

PR:		240339
Reported by:	imp, GregV, et al.
MFC after:	3 days
This commit is contained in:
wulf 2019-09-12 12:33:09 +00:00
parent bca4269344
commit 1d48a59583
1 changed files with 2 additions and 0 deletions
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2
sys/dev/ichiic/ig4_iic.c
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@ -590,6 +590,8 @@ ig4iic_attach(ig4iic_softc_t *sc)
reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
if (sc->version == IG4_SKYLAKE)
reg_write(sc, IG4_REG_SDA_HOLD, 28);
/*
* Use a threshold of 1 so we get interrupted on each character,